tree f685fb5a6c0d6ace4aceee3628fd3cd6c76a6caf
parent efd342fb0031a17758571dce42e3f373d94e2fec
author Matthias Brugger <matthias.bgg@gmail.com> 1405676203 +0200
committer Daniel Lezcano <daniel.lezcano@linaro.org> 1406109751 +0200

clocksource: Add support for the Mediatek SoCs

This patch adds a clock source and clock event for the timer found
on the Mediatek SoCs.

The Mediatek General Purpose Timer block provides five 32 bit timers and
one 64 bit timer.

Two 32 bit timers are used by this driver:
TIMER1: clock events supporting periodic and oneshot events
TIMER2: clock source configured as a free running counter

The General Purpose Timer block can be run with two clocks. A 13 MHz system
clock and the RTC clock running at 32 KHz. This implementation uses the system
clock with no clock source divider.

The interrupts are shared between the different timers and have to be read back
from a register. We just enable one interrupt for the clock event. The clock
event timer is used by all cores.

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>