tree 0c700acae95db629e0e085bc4608752e4f77b515
parent edaf3fb580df7f6c510699664f51485030a29f17
author Emilio López <emilio@elopez.com.ar> 1387769554 -0300
committer Emilio López <emilio@elopez.com.ar> 1388261286 -0300

clk: sunxi: add gating support to PLL1

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>