tree 4bea7383ecc81b2d87f891e2fe0587df5ffcf12d
parent e4d59f6b0f51d0c46fbd7e15a653045ad63161a8
author Rodrigo Vivi <rodrigo.vivi@intel.com> 1415983956 -0800
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1417595708 +0100

drm/i915: Add PSR registers for PSR VLV/CHV.

Baytrail (Valleyview) and Braswell (Cherryview) uses a complete different
implementation of PSR that we currently have supported for
Haswell and Broadwell. So let's start by adding registers definitions.

I usually don't like commit that adds just registers without using,
but after I put all in one commit I realized that no one would want
to take the AR to review it so I decided to split in order to make
reviewer's life easier. Only last commit in this series will actually
enable the PSR on intel enable panel path.

But as it happens currently with HSW/BDW the plan is to let it
disabled by default (protected by kernel parameter)
while we are able to fully validate it.

v2: Remove a unused bit definition that isn't used on vlv and
    reserved on chv as pointed out by Durgadoss.

Cc: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>