clk: samsung: pll: Use new registration method for PLL46xx
This patch modifies PLL46xx support code and its users to use the
recently introduced common PLL registration helper.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index fd0215d..779c206 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -985,11 +985,15 @@
{},
};
-static struct samsung_pll_clock exynos4210_plls[] __initdata = {
+static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
[apll] = PLL_A(pll_4508, fout_apll, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, "fout_apll", NULL),
[mpll] = PLL_A(pll_4508, fout_mpll, "fout_mpll", "fin_pll",
E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
+ [epll] = PLL_A(pll_4600, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK,
+ EPLL_CON0, "fout_epll", NULL),
+ [vpll] = PLL_A(pll_4650c, fout_vpll, "fout_vpll", "mout_vpllsrc",
+ VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
};
static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1008,8 +1012,6 @@
enum exynos4_soc exynos4_soc,
void __iomem *reg_base, unsigned long xom)
{
- struct clk *epll, *vpll;
-
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
@@ -1032,13 +1034,6 @@
if (exynos4_soc == EXYNOS4210) {
samsung_clk_register_pll(exynos4210_plls,
ARRAY_SIZE(exynos4210_plls), reg_base);
- epll = samsung_clk_register_pll46xx("fout_epll", "fin_pll",
- reg_base + EPLL_CON0, pll_4600);
- vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc",
- reg_base + VPLL_CON0, pll_4650c);
-
- samsung_clk_add_lookup(epll, fout_epll);
- samsung_clk_add_lookup(vpll, fout_vpll);
} else {
samsung_clk_register_pll(exynos4x12_plls,
ARRAY_SIZE(exynos4x12_plls), reg_base);