/*
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 * Authors: Thomas Abraham <thomas.ab@samsung.com>
 *         Chander Kashyap <k.chander@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Exynos8895 SoC.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/samsung/cal-if.h>
#include <dt-bindings/clock/exynos8895.h>

#include "../../soc/samsung/cal-if/exynos8895/cmucal-vclk.h"
#include "../../soc/samsung/cal-if/exynos8895/cmucal-node.h"
#include "../../soc/samsung/cal-if/exynos8895/cmucal-qch.h"
#include "../../soc/samsung/cal-if/exynos8895/clkout_exynos8895.h"
#include "composite.h"

static struct samsung_clk_provider *exynos8895_clk_privider;
/*
 * list of controller registers to be saved and restored during a
 * suspend/resume cycle.
 */
/* fixed rate clocks generated outside the soc */
struct samsung_fixed_rate exynos8895_fixed_rate_ext_clks[] __initdata = {
	FRATE(OSCCLK, "fin_pll", NULL, CLK_IS_ROOT, 26000000),
};

/* HWACG VCLK */
struct init_vclk exynos8895_abox_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_ABOX_CMU_ABOX, ABOX_CMU_ABOX_QCH, "GATE_ABOX_CMU_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_TOP, ABOX_TOP_QCH, "GATE_ABOX_TOP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_ABOX, BTM_ABOX_QCH, "GATE_BTM_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_ABOX, GPIO_ABOX_QCH, "GATE_GPIO_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_ABOX, PMU_ABOX_QCH, "GATE_PMU_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_ABOX, BCM_ABOX_QCH, "GATE_BCM_ABOX", NULL, 0, VCLK_GATE, "GATE_BCM_ABOX"),
	HWACG_VCLK(GATE_SMMU_ABOX, SMMU_ABOX_QCH, "GATE_SMMU_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_ABOX, SYSREG_ABOX_QCH, "GATE_SYSREG_ABOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_ABOXCPU, WDT_ABOXCPU_QCH, "GATE_WDT_ABOXCPU", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UAIF0, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0 , "GATE_UAIF0", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_UAIF1, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1 , "GATE_UAIF1", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_UAIF2, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2 , "GATE_UAIF2", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_UAIF3, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3 , "GATE_UAIF3", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_UAIF4, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4 , "GATE_UAIF4", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_DSIF, GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF, "GATE_DSIF", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
};

struct init_vclk exynos8895_apm_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_APM_BUS, MUX_CLKCMU_APM_BUS_USER, "UMUX_CLKCMU_APM_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_APM_SYS, APM_QCH_SYS, "GATE_APM_SYS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_APM_CPU, APM_QCH_CPU, "GATE_APM_CPU", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_APM_OSCCLK, APM_QCH_OSCCLK, "GATE_APM_OSCCLK", "fin_pll", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_APM_CMU_APM, APM_CMU_APM_QCH, "GATE_APM_CMU_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2AP, MAILBOX_APM2AP_QCH, "GATE_MAILBOX_APM2AP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2CP, MAILBOX_APM2CP_QCH, "GATE_MAILBOX_APM2CP", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM2GNSS, MAILBOX_APM2GNSS_QCH, "GATE_MAILBOX_APM2GNSS", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SCAN2AXI, SCAN2AXI_QCH, "GATE_SCAN2AXI", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_APM, SYSREG_APM_QCH, "GATE_SYSREG_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", "UMUX_CLKCMU_APM_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_bus1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_BUS1_BUS, MUX_CLKCMU_BUS1_BUS_USER, "UMUX_CLKCMU_BUS1_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BUS1_CMU_BUS1, BUS1_CMU_BUS1_QCH, "GATE_BUS1_CMU_BUS1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_BUS1, PMU_BUS1_QCH, "GATE_PMU_BUS1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_BUS1, SYSREG_BUS1_QCH, "GATE_SYSREG_BUS1", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_busc_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS_USER, "UMUX_CLKCMU_BUSC_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_BUSC_BUSPHSI2C, MUX_CLKCMU_BUSC_BUSPHSI2C_USER, "UMUX_CLKCMU_BUSC_BUSPHSI2C", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_ADCIF_BUSC_S0, ADCIF_BUSC_QCH_S0, "GATE_ADCIF_BUSC_S0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ADCIF_BUSC_S1, ADCIF_BUSC_QCH_S1, "GATE_ADCIF_BUSC_S1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BUSC_CMU_BUSC, BUSC_CMU_BUSC_QCH, "GATE_BUSC_CMU_BUSC", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BUSIF_CMUTOPC, BUSIF_CMUTOPC_QCH, "GATE_BUSIF_CMUTOPC", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GNSSMBOX, GNSSMBOX_QCH, "GATE_GNSSMBOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_BUSC, GPIO_BUSC_QCH, "GATE_GPIO_BUSC", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2CDF, HSI2CDF_QCH, "GATE_HSI2CDF", "UMUX_CLKCMU_BUSC_BUSPHSI2C", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MBOX, MBOX_QCH, "GATE_MBOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PDMA0, PDMA0_QCH, "GATE_PDMA0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_BUSC, PMU_BUSC_QCH, "GATE_PMU_BUSC", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SECMBOX, SECMBOX_QCH, "GATE_SECMBOX", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPDMA, SPDMA_QCH, "GATE_SPDMA", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY, SPEEDY_QCH, "GATE_SPEEDY", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_SPEEDY, SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_SPEEDY", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_CP, SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_CP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP, SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, "GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_BUSC, SYSREG_BUSC_QCH, "GATE_SYSREG_BUSC", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_cam_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_CAM_BUS, MUX_CLKCMU_CAM_BUS_USER, "UMUX_CLKCMU_CAM_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_CAM_TPU0, MUX_CLKCMU_CAM_TPU0_USER, "UMUX_CLKCMU_CAM_TPU0", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_CAM_VRA, MUX_CLKCMU_CAM_VRA_USER, "UMUX_CLKCMU_CAM_VRA", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_CAM_TPU1, MUX_CLKCMU_CAM_TPU1_USER, "UMUX_CLKCMU_CAM_TPU1", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_CAMD0, BTM_CAMD0_QCH, "GATE_BTM_CAMD0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_CAMD1, BTM_CAMD1_QCH, "GATE_BTM_CAMD1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_CAM_CMU_CAM, CAM_CMU_CAM_QCH, "GATE_CAM_CMU_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ISP_EWGEN_CAM, ISP_EWGEN_CAM_QCH, "GATE_ISP_EWGEN_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_CSIS0, IS_CAM_QCH_CSIS0, "GATE_IS_CAM_CSIS0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_CSIS1, IS_CAM_QCH_CSIS1, "GATE_IS_CAM_CSIS1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_CSIS2, IS_CAM_QCH_CSIS2, "GATE_IS_CAM_CSIS2", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_CSIS3, IS_CAM_QCH_CSIS3, "GATE_IS_CAM_CSIS3", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_MC_SCALER, IS_CAM_QCH_MC_SCALER, "GATE_IS_CAM_MC_SCALER", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_CSISX4_DMA, IS_CAM_QCH_CSISX4_DMA, "GATE_IS_CAM_CSISX4_DMA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_SYSMMU_CAM0, IS_CAM_QCH_SYSMMU_CAM0, "GATE_IS_CAM_SYSMMU_CAM0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_SYSMMU_CAM1, IS_CAM_QCH_SYSMMU_CAM1, "GATE_IS_CAM_SYSMMU_CAM1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_BCM_CAM0, IS_CAM_QCH_BCM_CAM0, "GATE_IS_CAM_BCM_CAM0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, "GATE_BCM_CAM0"),
	HWACG_VCLK(GATE_IS_CAM_BCM_CAM1, IS_CAM_QCH_BCM_CAM1, "GATE_IS_CAM_BCM_CAM1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, "GATE_BCM_CAM1"),
	HWACG_VCLK(GATE_IS_CAM_QE_TPU0, IS_CAM_QCH_QE_TPU0, "GATE_IS_CAM_QE_TPU0", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_QE_VRA, IS_CAM_QCH_QE_VRA, "GATE_IS_CAM_QE_VRA", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_BNS, IS_CAM_QCH_BNS, "GATE_IS_CAM_BNS", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_QE_CSISX4, IS_CAM_QCH_QE_CSISX4, "GATE_IS_CAM_QE_CSISX4", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_QE_TPU1, IS_CAM_QCH_QE_TPU1, "GATE_IS_CAM_QE_TPU1", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_CAM, PMU_CAM_QCH, "GATE_PMU_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_CAM, SYSREG_CAM_QCH, "GATE_SYSREG_CAM", "UMUX_CLKCMU_CAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_TPU0, IS_CAM_QCH_TPU0, "GATE_IS_CAM_TPU0", "UMUX_CLKCMU_CAM_TPU0", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_VRA, IS_CAM_QCH_VRA, "GATE_IS_CAM_VRA", "UMUX_CLKCMU_CAM_VRA", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_CAM_TPU1, IS_CAM_QCH_TPU1, "GATE_IS_CAM_TPU1", "UMUX_CLKCMU_CAM_TPU1", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_cmu_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_CMU_CMU_CMUREF, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMU_CMUREF", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_DFTMUX_TOP_CIS_CLK0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_DFTMUX_TOP_CIS_CLK1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_DFTMUX_TOP_CIS_CLK2", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_DFTMUX_TOP_CIS_CLK3", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_dcam_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DCAM_BUS, MUX_CLKCMU_DCAM_BUS_USER, "UMUX_CLKCMU_DCAM_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_DCAM_IMGD, MUX_CLKCMU_DCAM_IMGD_USER, "UMUX_CLKCMU_DCAM_IMGD", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_DCAM, BTM_DCAM_QCH, "GATE_BTM_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DCAM_CMU_DCAM, DCAM_CMU_DCAM_QCH, "GATE_DCAM_CMU_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DCP, DCP_QCH, "GATE_DCP", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_DCAM, PMU_DCAM_QCH, "GATE_PMU_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_DCAM, BCM_DCAM_QCH, "GATE_BCM_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, "GATE_BCM_DCAM"),
	HWACG_VCLK(GATE_SYSREG_DCAM, SYSREG_DCAM_QCH, "GATE_SYSREG_DCAM", "UMUX_CLKCMU_DCAM_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_dpu0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS_USER, "UMUX_CLKCMU_DPU_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_DPUD0, BTM_DPUD0_QCH, "GATE_BTM_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_DPUD1, BTM_DPUD1_QCH, "GATE_BTM_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_DPUD2, BTM_DPUD2_QCH, "GATE_BTM_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DECON0, DECON0_QCH, "GATE_DECON0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPP_DPP_G0, DPP_QCH_DPP_G0, "GATE_DPP_DPP_G0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPP_DPP_G1, DPP_QCH_DPP_G1, "GATE_DPP_DPP_G1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPP_DPP_VGR, DPP_QCH_DPP_VGR, "GATE_DPP_DPP_VGR", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU0_CMU_DPU0, DPU0_CMU_DPU0_QCH, "GATE_DPU0_CMU_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DMA, DPU_DMA_QCH, "GATE_DPU_DMA", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_WB_MUX, DPU_WB_MUX_QCH, "GATE_DPU_WB_MUX", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_DPU0, PMU_DPU0_QCH, "GATE_PMU_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_DPUD0, BCM_DPUD0_QCH, "GATE_BCM_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU0"),
	HWACG_VCLK(GATE_BCM_DPUD1, BCM_DPUD1_QCH, "GATE_BCM_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU1"),
	HWACG_VCLK(GATE_BCM_DPUD2, BCM_DPUD2_QCH, "GATE_BCM_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, "GATE_BCM_DPU2"),
	HWACG_VCLK(GATE_SYSMMU_DPUD0, SYSMMU_DPUD0_QCH, "GATE_SYSMMU_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DPUD1, SYSMMU_DPUD1_QCH, "GATE_SYSMMU_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DPUD2, SYSMMU_DPUD2_QCH, "GATE_SYSMMU_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_DPU0, SYSREG_DPU0_QCH, "GATE_SYSREG_DPU0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_dpu1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DPU1_BUSD, MUX_CLKCMU_DPU1_BUSD_USER, "UMUX_CLKCMU_DPU1_BUSD", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_DPU1_BUSP, MUX_CLKCMU_DPU1_BUSP_USER, "UMUX_CLKCMU_DPU1_BUSP", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_DECON1, DECON1_QCH, "GATE_DECON1", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DECON2_ACLK, DECON2_QCH_ACLK, "GATE_DECON2_ACLK", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DECON2_VCLK, DECON2_QCH_VCLK, "GATE_DECON2_VCLK", "UMUX_CLKCMU_DPU1_BUSD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU1_CMU_DPU1, DPU1_CMU_DPU1_QCH, "GATE_DPU1_CMU_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_DPU1, PMU_DPU1_QCH, "GATE_PMU_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_DPU1, SYSREG_DPU1_QCH, "GATE_SYSREG_DPU1", "UMUX_CLKCMU_DPU1_BUSP", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_dsp_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DSP_BUS, MUX_CLKCMU_DSP_BUS_USER, "UMUX_CLKCMU_DSP_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_SCORE, BTM_SCORE_QCH, "GATE_BTM_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DSP_CMU_DSP, DSP_CMU_DSP_QCH, "GATE_DSP_CMU_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_DSP, PMU_DSP_QCH, "GATE_PMU_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_SCORE, BCM_SCORE_QCH, "GATE_BCM_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, "GATE_BCM_SCORE"),
	HWACG_VCLK(GATE_SCORE, SCORE_QCH, "GATE_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_SCORE, SMMU_SCORE_QCH, "GATE_SMMU_SCORE", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_DSP, SYSREG_DSP_QCH, "GATE_SYSREG_DSP", "UMUX_CLKCMU_DSP_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_fsys0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS_USER, "UMUX_CLKCMU_FSYS0_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC_USER, "UMUX_CLKCMU_FSYS0_DPGTC", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_UFS_EMBD, MUX_CLKCMU_FSYS0_UFS_EMBD_USER, "UMUX_CLKCMU_FSYS0_UFS_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_MMC_EMBD, MUX_CLKCMU_FSYS0_MMC_EMBD_USER, "UMUX_CLKCMU_FSYS0_MMC_EMBD", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_USBDRD30, MUX_CLKCMU_FSYS0_USBDRD30_USER, "UMUX_CLKCMU_FSYS0_USBDRD30", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_FSYS0, BTM_FSYS0_QCH, "GATE_BTM_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ETR_MIU_PCLK, ETR_MIU_QCH_PCLK, "GATE_ETR_MIU_PCLK", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ETR_MIU_ACLK, ETR_MIU_QCH_ACLK, "GATE_ETR_MIU_ACLK", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_FSYS0_CMU_FSYS0, FSYS0_CMU_FSYS0_QCH, "GATE_FSYS0_CMU_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_FSYS0, GPIO_FSYS0_QCH, "GATE_GPIO_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_FSYS0, PMU_FSYS0_QCH, "GATE_PMU_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_FSYS0, BCM_FSYS0_QCH, "GATE_BCM_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, "GATE_BCM_FSYS0"),
	HWACG_VCLK(GATE_SYSREG_FSYS0, SYSREG_FSYS0_QCH, "GATE_SYSREG_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_EMBD_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_FMP", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USBTV_USBTV_HOST, USBTV_QCH_USBTV_HOST, "GATE_USBTV_USBTV_HOST", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DP_LINK, DP_LINK_QCH, "GATE_DP_LINK", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_EMBD, UFS_EMBD_QCH, "GATE_UFS_EMBD", "UMUX_CLKCMU_FSYS0_UFS_EMBD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MMC_EMBD, MMC_EMBD_QCH, "GATE_MMC_EMBD", "UMUX_CLKCMU_FSYS0_MMC_EMBD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USBTV_USB30DRD_LINK, USBTV_QCH_USB30DRD_LINK, "GATE_USBTV_USB30DRD_LINK", "UMUX_CLKCMU_FSYS0_USBDRD30", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_fsys1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS_USER, "UMUX_CLKCMU_FSYS1_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD_USER, "UMUX_CLKCMU_FSYS1_MMC_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD_USER, "UMUX_CLKCMU_FSYS1_UFS_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE_USER, "UMUX_CLKCMU_FSYS1_PCIE", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_ADM_AHB_SSS, ADM_AHB_SSS_QCH, "GATE_ADM_AHB_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_FSYS1, BTM_FSYS1_QCH, "GATE_BTM_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_FSYS1_CMU_FSYS1, FSYS1_CMU_FSYS1_QCH, "GATE_FSYS1_CMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_FSYS1, GPIO_FSYS1_QCH, "GATE_GPIO_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE0_MSTR, PCIE_QCH_PCIE0_MSTR, "GATE_PCIE_PCIE0_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE_PCS, PCIE_QCH_PCIE_PCS, "GATE_PCIE_PCIE_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE_PHY, PCIE_QCH_PCIE_PHY, "GATE_PCIE_PCIE_PHY", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE0_DBI, PCIE_QCH_PCIE0_DBI, "GATE_PCIE_PCIE0_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE0_APB, PCIE_QCH_PCIE0_APB, "GATE_PCIE_PCIE0_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	/* PCIE ref_clk don't have QCH */
	HWACG_VCLK(GATE_PCIE_PCIE_SOCPLL, PCIE_QCH_PCIE_SOCPLL, "GATE_PCIE_PCIE_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE1_MSTR, PCIE_QCH_PCIE1_MSTR, "GATE_PCIE_PCIE1_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE1_DBI, PCIE_QCH_PCIE1_DBI, "GATE_PCIE_PCIE1_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_PCIE1_APB, PCIE_QCH_PCIE1_APB, "GATE_PCIE_PCIE1_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_FSYS1, PMU_FSYS1_QCH, "GATE_PMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_FSYS1, BCM_FSYS1_QCH, "GATE_BCM_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, "GATE_BCM_FSYS1"),
	HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_FSYS1, SYSREG_FSYS1_QCH, "GATE_SYSREG_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TOE_WIFI0, TOE_WIFI0_QCH, "GATE_TOE_WIFI0", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TOE_WIFI1, TOE_WIFI1_QCH, "GATE_TOE_WIFI1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_CARD_FMP, UFS_CARD_QCH_FMP, "GATE_UFS_CARD_FMP", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS1_MMC_CARD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_CARD, UFS_CARD_QCH, "GATE_UFS_CARD", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_g2d_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_G2D_JPEG, MUX_CLKCMU_G2D_JPEG_USER, "UMUX_CLKCMU_G2D_JPEG", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "UMUX_CLKCMU_G2D_G2D", "UMUX_CLKCMU_G2D_JPEG", 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_G2DD0, BTM_G2DD0_QCH, "GATE_BTM_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_G2DD1, BTM_G2DD1_QCH, "GATE_BTM_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_G2D_CMU_G2D, G2D_CMU_G2D_QCH, "GATE_G2D_CMU_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_G2D, PMU_G2D_QCH, "GATE_PMU_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_G2DD0, BCM_G2DD0_QCH, "GATE_BCM_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, "GATE_BCM_G2D0"),
	HWACG_VCLK(GATE_BCM_G2DD1, BCM_G2DD1_QCH, "GATE_BCM_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, "GATE_BCM_G2D1"),
	HWACG_VCLK(GATE_SMMU_G2DD0, SMMU_G2DD0_QCH, "GATE_SMMU_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_G2DD1, SMMU_G2DD1_QCH, "GATE_SMMU_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_G2D, SYSREG_G2D_QCH, "GATE_SYSREG_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_M2MSCALER, M2MSCALER_QCH, "GATE_M2MSCALER", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_G2DD2, BTM_G2DD2_QCH, "GATE_BTM_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_QE_JPEG, QE_JPEG_QCH, "GATE_QE_JPEG", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_QE_M2MSCALER, QE_M2MSCALER_QCH, "GATE_QE_M2MSCALER", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_G2DD2, BCM_G2DD2_QCH, "GATE_BCM_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, "GATE_BCM_G2D2"),
	HWACG_VCLK(GATE_SMMU_G2DD2, SMMU_G2DD2_QCH, "GATE_SMMU_G2DD2", "UMUX_CLKCMU_G2D_JPEG", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_g3d_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_AGPU_G3D, AGPU_QCH_G3D, "GATE_AGPU_G3D", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BUSIF_HPMG3D, BUSIF_HPMG3D_QCH, "GATE_BUSIF_HPMG3D", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_G3D_CMU_G3D, G3D_CMU_G3D_QCH, "GATE_G3D_CMU_G3D", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_G3D, PMU_G3D_QCH, "GATE_PMU_G3D", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_G3D, SYSREG_G3D_QCH, "GATE_SYSREG_G3D", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_imem_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_IMEM_BUS, MUX_CLKCMU_IMEM_BUS_USER, "UMUX_CLKCMU_IMEM_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_IMEM_CMU_IMEM, IMEM_CMU_IMEM_QCH, "GATE_IMEM_CMU_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_INTMEM, INTMEM_QCH, "GATE_INTMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_IMEM, PMU_IMEM_QCH, "GATE_PMU_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_IMEM, SYSREG_IMEM_QCH, "GATE_SYSREG_IMEM", "UMUX_CLKCMU_IMEM_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_isphq_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS_USER, "UMUX_CLKCMU_ISPHQ_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_ISPHQ_CMU_ISPHQ, ISPHQ_CMU_ISPHQ_QCH, "GATE_ISPHQ_CMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ISP_EWGEN_ISPHQ, ISP_EWGEN_ISPHQ_QCH, "GATE_ISP_EWGEN_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_3AA, IS_ISPHQ_QCH_3AA, "GATE_IS_ISPHQ_3AA", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_ISPHQ, IS_ISPHQ_QCH_ISPHQ, "GATE_IS_ISPHQ_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_QE_3AA, IS_ISPHQ_QCH_QE_3AA, "GATE_IS_ISPHQ_QE_3AA", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_QE_ISPHQ, IS_ISPHQ_QCH_QE_ISPHQ, "GATE_IS_ISPHQ_QE_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_ISPHQ, PMU_ISPHQ_QCH, "GATE_PMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_ISPHQ, SYSREG_ISPHQ_QCH, "GATE_SYSREG_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_isplq_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS_USER, "UMUX_CLKCMU_ISPLP_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_ISPLP, BTM_ISPLP_QCH, "GATE_BTM_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ISPLP_CMU_ISPLP, ISPLP_CMU_ISPLP_QCH, "GATE_ISPLP_CMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ISP_EWGEN_ISPLP, ISP_EWGEN_ISPLP_QCH, "GATE_ISP_EWGEN_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_3AAW, IS_ISPLP_QCH_3AAW, "GATE_IS_ISPLP_3AAW", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_ISPLP, IS_ISPLP_QCH_ISPLP, "GATE_IS_ISPLP_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_QE_3AAW, IS_ISPLP_QCH_QE_3AAW, "GATE_IS_ISPLP_QE_3AAW", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_QE_ISPLP, IS_ISPLP_QCH_QE_ISPLP, "GATE_IS_ISPLP_QE_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_SMMU_ISPLP, IS_ISPLP_QCH_SMMU_ISPLP, "GATE_IS_ISPLP_SMMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_BCM_ISPLP, IS_ISPLP_QCH_BCM_ISPLP, "GATE_IS_ISPLP_BCM_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, "GATE_BCM_ISPLP"),
	HWACG_VCLK(GATE_PMU_ISPLP, PMU_ISPLP_QCH, "GATE_PMU_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_ISPLP, SYSREG_ISPLP_QCH, "GATE_SYSREG_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_iva_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS_USER, "UMUX_CLKCMU_IVA_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_IVA, BTM_IVA_QCH, "GATE_BTM_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IVA, IVA_QCH, "GATE_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IVA_CMU_IVA, IVA_CMU_IVA_QCH, "GATE_IVA_CMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IVA_INTMEM, IVA_INTMEM_QCH, "GATE_IVA_INTMEM", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_IVA, PMU_IVA_QCH, "GATE_PMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_IVA, BCM_IVA_QCH, "GATE_BCM_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, "GATE_BCM_IVA"),
	HWACG_VCLK(GATE_SMMU_IVA, SMMU_IVA_QCH, "GATE_SMMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_IVA, SYSREG_IVA_QCH, "GATE_SYSREG_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_mfc_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_MFC_BUS, MUX_CLKCMU_MFC_BUS_USER, "UMUX_CLKCMU_MFC_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_MFCD0, BTM_MFCD0_QCH, "GATE_BTM_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_MFCD1, BTM_MFCD1_QCH, "GATE_BTM_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MFC_CMU_MFC, MFC_CMU_MFC_QCH, "GATE_MFC_CMU_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_MFC, PMU_MFC_QCH, "GATE_PMU_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_MFCD0, BCM_MFCD0_QCH, "GATE_BCM_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, "GATE_BCM_MFC0"),
	HWACG_VCLK(GATE_BCM_MFCD1, BCM_MFCD1_QCH, "GATE_BCM_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, "GATE_BCM_MFC1"),
	HWACG_VCLK(GATE_SMMU_MFCD0, SMMU_MFCD0_QCH, "GATE_SMMU_MFCD0", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_MFCD1, SMMU_MFCD1_QCH, "GATE_SMMU_MFCD1", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_MFC, SYSREG_MFC_QCH, "GATE_SYSREG_MFC", "UMUX_CLKCMU_MFC_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_peric0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_UART_DBG, MUX_CLKCMU_PERIC0_UART_DBG_USER, "UMUX_CLKCMU_PERIC0_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI00, MUX_CLKCMU_PERIC0_USI00_USER, "UMUX_CLKCMU_PERIC0_USI00", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI01, MUX_CLKCMU_PERIC0_USI01_USER, "UMUX_CLKCMU_PERIC0_USI01", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI02, MUX_CLKCMU_PERIC0_USI02_USER, "UMUX_CLKCMU_PERIC0_USI02", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI03, MUX_CLKCMU_PERIC0_USI03_USER, "UMUX_CLKCMU_PERIC0_USI03", "UMUX_CLKCMU_PERIC0_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_GPIO_PERIC0, GPIO_PERIC0_QCH, "GATE_GPIO_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PERIC0_CMU_PERIC0, PERIC0_CMU_PERIC0_QCH, "GATE_PERIC0_CMU_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_PERIC0, PMU_PERIC0_QCH, "GATE_PMU_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PWM, PWM_QCH, "GATE_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_TSP, SPEEDY2_TSP_QCH, "GATE_SPEEDY2_TSP", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_PERIC0, SYSREG_PERIC0_QCH, "GATE_SYSREG_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UART_DBG, UART_DBG_QCH, "GATE_UART_DBG", "UMUX_CLKCMU_PERIC0_UART_DBG", 0, VCLK_GATE, "console-pclk0"),
	HWACG_VCLK(GATE_USI00, USI00_QCH, "GATE_USI00", "UMUX_CLKCMU_PERIC0_USI00", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI01, USI01_QCH, "GATE_USI01", "UMUX_CLKCMU_PERIC0_USI01", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI02, USI02_QCH, "GATE_USI02", "UMUX_CLKCMU_PERIC0_USI02", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI03, USI03_QCH, "GATE_USI03", "UMUX_CLKCMU_PERIC0_USI03", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_peric1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_UART_BT, MUX_CLKCMU_PERIC1_UART_BT_USER, "UMUX_CLKCMU_PERIC1_UART_BT", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI04, MUX_CLKCMU_PERIC1_USI04_USER, "UMUX_CLKCMU_PERIC1_USI04", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI05, MUX_CLKCMU_PERIC1_USI05_USER, "UMUX_CLKCMU_PERIC1_USI05", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI06, MUX_CLKCMU_PERIC1_USI06_USER, "UMUX_CLKCMU_PERIC1_USI06", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI07, MUX_CLKCMU_PERIC1_USI07_USER, "UMUX_CLKCMU_PERIC1_USI07", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI08, MUX_CLKCMU_PERIC1_USI08_USER, "UMUX_CLKCMU_PERIC1_USI08", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI09, MUX_CLKCMU_PERIC1_USI09_USER, "UMUX_CLKCMU_PERIC1_USI09", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI10, MUX_CLKCMU_PERIC1_USI10_USER, "UMUX_CLKCMU_PERIC1_USI10", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI11, MUX_CLKCMU_PERIC1_USI11_USER, "UMUX_CLKCMU_PERIC1_USI11", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI12, MUX_CLKCMU_PERIC1_USI12_USER, "UMUX_CLKCMU_PERIC1_USI12", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI13, MUX_CLKCMU_PERIC1_USI13_USER, "UMUX_CLKCMU_PERIC1_USI13", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPI_CAM0, MUX_CLKCMU_PERIC1_SPI_CAM0_USER, "UMUX_CLKCMU_PERIC1_SPI_CAM0", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPI_CAM1, MUX_CLKCMU_PERIC1_SPI_CAM1_USER, "UMUX_CLKCMU_PERIC1_SPI_CAM1", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_SPEEDY2, MUX_CLKCMU_PERIC1_SPEEDY2_USER, "UMUX_CLKCMU_PERIC1_SPEEDY2", "UMUX_CLKCMU_PERIC1_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_GPIO_PERIC1, GPIO_PERIC1_QCH, "GATE_GPIO_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C_CAM0, HSI2C_CAM0_QCH, "GATE_HSI2C_CAM0", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C_CAM1, HSI2C_CAM1_QCH, "GATE_HSI2C_CAM1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C_CAM2, HSI2C_CAM2_QCH, "GATE_HSI2C_CAM2", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HSI2C_CAM3, HSI2C_CAM3_QCH, "GATE_HSI2C_CAM3", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PERIC1_CMU_PERIC1, PERIC1_CMU_PERIC1_QCH, "GATE_PERIC1_CMU_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_PERIC1, PMU_PERIC1_QCH, "GATE_PMU_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_TSP1, SPEEDY2_TSP1_QCH, "GATE_SPEEDY2_TSP1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_TSP2, SPEEDY2_TSP2_QCH, "GATE_SPEEDY2_TSP2", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_PERIC1, SYSREG_PERIC1_QCH, "GATE_SYSREG_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UART_BT, UART_BT_QCH, "GATE_UART_BT", "UMUX_CLKCMU_PERIC1_UART_BT", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI04, USI04_QCH, "GATE_USI04", "UMUX_CLKCMU_PERIC1_USI04", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI05, USI05_QCH, "GATE_USI05", "UMUX_CLKCMU_PERIC1_USI05", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI06, USI06_QCH, "GATE_USI06", "UMUX_CLKCMU_PERIC1_USI06", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI07, USI07_QCH, "GATE_USI07", "UMUX_CLKCMU_PERIC1_USI07", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI08, USI08_QCH, "GATE_USI08", "UMUX_CLKCMU_PERIC1_USI08", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI09, USI09_QCH, "GATE_USI09", "UMUX_CLKCMU_PERIC1_USI09", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI10, USI10_QCH, "GATE_USI10", "UMUX_CLKCMU_PERIC1_USI10", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI11, USI11_QCH, "GATE_USI11", "UMUX_CLKCMU_PERIC1_USI11", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI12, USI12_QCH, "GATE_USI12", "UMUX_CLKCMU_PERIC1_USI12", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI13, USI13_QCH, "GATE_USI13", "UMUX_CLKCMU_PERIC1_USI13", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPI_CAM0, SPI_CAM0_QCH, "GATE_SPI_CAM0", "UMUX_CLKCMU_PERIC1_SPI_CAM0", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPI_CAM1, SPI_CAM1_QCH, "GATE_SPI_CAM1", "UMUX_CLKCMU_PERIC1_SPI_CAM1", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_DDI, SPEEDY2_DDI_QCH, "GATE_SPEEDY2_DDI", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_DDI1, SPEEDY2_DDI1_QCH, "GATE_SPEEDY2_DDI1", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY2_DDI2, SPEEDY2_DDI2_QCH, "GATE_SPEEDY2_DDI2", "UMUX_CLKCMU_PERIC1_SPEEDY2", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_peris_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BUSIF_TMU, BUSIF_TMU_QCH, "GATE_BUSIF_TMU", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GIC, GIC_QCH, "GATE_GIC", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_BIRA, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PERIS_CMU_PERIS, PERIS_CMU_PERIS_QCH, "GATE_PERIS_CMU_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_PERIS, PMU_PERIS_QCH, "GATE_PMU_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_PERIS, SYSREG_PERIS_QCH, "GATE_SYSREG_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC00, TZPC00_QCH, "GATE_TZPC00", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC01, TZPC01_QCH, "GATE_TZPC01", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC02, TZPC02_QCH, "GATE_TZPC02", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC03, TZPC03_QCH, "GATE_TZPC03", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC04, TZPC04_QCH, "GATE_TZPC04", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC05, TZPC05_QCH, "GATE_TZPC05", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC06, TZPC06_QCH, "GATE_TZPC06", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC07, TZPC07_QCH, "GATE_TZPC07", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC08, TZPC08_QCH, "GATE_TZPC08", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC09, TZPC09_QCH, "GATE_TZPC09", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC10, TZPC10_QCH, "GATE_TZPC10", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC11, TZPC11_QCH, "GATE_TZPC11", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC12, TZPC12_QCH, "GATE_TZPC12", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC13, TZPC13_QCH, "GATE_TZPC13", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC14, TZPC14_QCH, "GATE_TZPC14", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TZPC15, TZPC15_QCH, "GATE_TZPC15", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER1, WDT_CLUSTER1_QCH, "GATE_WDT_CLUSTER1", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_srdz_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_SRDZ_BUS, MUX_CLKCMU_SRDZ_BUS_USER, "UMUX_CLKCMU_SRDZ_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_SRDZ_IMGD, MUX_CLKCMU_SRDZ_IMGD_USER, "UMUX_CLKCMU_SRDZ_IMGD", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_SRDZ, BTM_SRDZ_QCH, "GATE_BTM_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_SRDZ, PMU_SRDZ_QCH, "GATE_PMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_SRDZ, BCM_SRDZ_QCH, "GATE_BCM_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, "GATE_BCM_SRDZ"),
	HWACG_VCLK(GATE_SMMU_SRDZ, SMMU_SRDZ_QCH, "GATE_SMMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SRDZ, SRDZ_QCH, "GATE_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SRDZ_CMU_SRDZ, SRDZ_CMU_SRDZ_QCH, "GATE_SRDZ_CMU_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_SRDZ, SYSREG_SRDZ_QCH, "GATE_SYSREG_SRDZ", "UMUX_CLKCMU_SRDZ_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_vpu_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_VPU_BUS, MUX_CLKCMU_VPU_BUS_USER, "UMUX_CLKCMU_VPU_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_BTM_VPU, BTM_VPU_QCH, "GATE_BTM_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_VPU, PMU_VPU_QCH, "GATE_PMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BCM_VPU, BCM_VPU_QCH, "GATE_BCM_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, "GATE_BCM_VPU"),
	HWACG_VCLK(GATE_SMMU_VPU, SMMU_VPU_QCH, "GATE_SMMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_VPU, SYSREG_VPU_QCH, "GATE_SYSREG_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VPU, VPU_QCH, "GATE_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VPU_CMU_VPU, VPU_CMU_VPU_QCH, "GATE_VPU_CMU_VPU", "UMUX_CLKCMU_VPU_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos8895_vts_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_OSC_VTS, OSC_VTS, "GATE_OSC_VTS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_CMU_VTS_CMUREF, CMU_VTS_CMUREF_QCH, "GATE_CMU_VTS_CMUREF", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_AHB, DMIC_AHB_QCH_PCLK, "GATE_DMIC_AHB", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_AHB_HCLK, DMIC_AHB_QCH_HCLK, "GATE_DMIC_AHB_HCLK", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF, DMIC_IF_QCH_PCLK, "GATE_DMIC_IF", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF_DMIC_CLK, DMIC_IF_QCH_DMIC_CLK, "GATE_DMIC_IF_DMIC_CLK", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_VTS, GPIO_VTS_QCH, "GATE_GPIO_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_VTS2AP, MAILBOX_VTS2AP_QCH, "GATE_MAILBOX_VTS2AP", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_VTS, SYSREG_VTS_QCH, "GATE_SYSREG_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VTS_CPU, VTS_QCH_CPU, "GATE_VTS_CPU", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VTS_SYS, VTS_QCH_SYS, "GATE_VTS_SYS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VTS_SYS_DMIC, VTS_QCH_SYS_DMIC, "GATE_VTS_SYS_DMIC", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VTS_CMU_VTS, VTS_CMU_VTS_QCH, "GATE_VTS_CMU_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_VTS, WDT_VTS_QCH, "GATE_WDT_VTS", "GATE_OSC_VTS", 0, VCLK_GATE, NULL),
};

static struct init_vclk exynos8895_clkout_vclks[] __initdata = {
	VCLK(OSCCLK_NFC, VCLK_CLKOUT1, "OSCCLK_NFC", 0, 0, NULL),
	VCLK(OSCCLK_AUD, VCLK_CLKOUT0, "OSCCLK_AUD", 0, 0, NULL),
};

/* Special VCLK */
struct init_vclk exynos8895_abox_vclks[] __initdata = {
	VCLK(ABOX_CPU_PCLKDBG, VCLK_SPL_CLK_ABOX_CPU_PCLKDBG_BLK_ABOX, "ABOX_CPU_PCLKDBG", 0, 0, NULL),
	VCLK(ABOX_UAIF0, VCLK_SPL_CLK_ABOX_UAIF0_BLK_ABOX, "ABOX_UAIF0", 0, 0, NULL),
	VCLK(ABOX_UAIF1, VCLK_SPL_CLK_ABOX_UAIF1_BLK_ABOX, "ABOX_UAIF1", 0, 0, NULL),
	VCLK(ABOX_UAIF2, VCLK_SPL_CLK_ABOX_UAIF2_BLK_ABOX, "ABOX_UAIF2", 0, 0, NULL),
	VCLK(ABOX_UAIF3, VCLK_SPL_CLK_ABOX_UAIF3_BLK_ABOX, "ABOX_UAIF3", 0, 0, NULL),
	VCLK(ABOX_UAIF4, VCLK_SPL_CLK_ABOX_UAIF4_BLK_ABOX, "ABOX_UAIF4", 0, 0, NULL),
	VCLK(ABOX_CPU_ACLK, VCLK_SPL_CLK_ABOX_CPU_ACLK_BLK_ABOX, "ABOX_CPU_ACLK", 0, 0, NULL),
	VCLK(ABOX_DMIC, VCLK_DIV_CLK_ABOX_DMIC_BLK_ABOX,  "ABOX_DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_AUDIF, DIV_CLK_ABOX_AUDIF, "DOUT_CLK_ABOX_AUDIF", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_DSIF, DIV_CLK_ABOX_DSIF, "DOUT_CLK_ABOX_DSIF", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_DMIC, DIV_CLK_ABOX_DMIC, "DOUT_CLK_ABOX_DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF0, DIV_CLK_ABOX_UAIF0, "DOUT_CLK_ABOX_UAIF0", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF1, DIV_CLK_ABOX_UAIF1, "DOUT_CLK_ABOX_UAIF1", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF2, DIV_CLK_ABOX_UAIF2, "DOUT_CLK_ABOX_UAIF2", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF3, DIV_CLK_ABOX_UAIF3, "DOUT_CLK_ABOX_UAIF3", 0, 0, NULL),
	VCLK(DOUT_CLK_ABOX_UAIF4, DIV_CLK_ABOX_UAIF4, "DOUT_CLK_ABOX_UAIF4", 0, 0, NULL),
	VCLK(PLL_OUT_AUD, PLL_AUD, "PLL_OUT_AUD", 0, 0, NULL),
};

struct init_vclk exynos8895_fsys0_vclks[] __initdata = {
	VCLK(MMC_EMBD, VCLK_SPL_CLK_FSYS0_MMC_EMBD_BLK_CMU, "MMC_EMBD", 0, 0, NULL),
	VCLK(DPGTC, VCLK_SPL_CLK_FSYS0_DPGTC_BLK_CMU, "DPGTC", 0, 0, NULL),
	VCLK(UFS_EMBD, VCLK_SPL_CLK_FSYS0_UFS_EMBD_BLK_CMU, "UFS_EMBD", 0, 0, NULL),
	VCLK(USBDRD30, VCLK_SPL_CLK_FSYS0_USBDRD30_BLK_CMU, "USBDRD30", 0, 0, NULL),
};

struct init_vclk exynos8895_fsys1_vclks[] __initdata = {
	VCLK(MMC_CARD, VCLK_SPL_CLK_FSYS1_MMC_CARD_BLK_CMU, "MMC_CARD", 0, 0, NULL),
	VCLK(UFS_CARD, VCLK_SPL_CLK_FSYS1_UFS_CARD_BLK_CMU, "UFS_CARD", 0, 0, NULL),
	VCLK(PCIE, VCLK_OCC_CLK_FSYS1_PCIE_BLK_CMU, "PCIE", 0, 0, NULL),
};

struct init_vclk exynos8895_peric0_vclks[] __initdata = {
	VCLK(UART_DBG, VCLK_SPL_CLK_PERIC0_UART_DBG_BLK_CMU, "UART_DBG", 0, 0, "console-sclk0"),
	VCLK(USI00, VCLK_SPL_CLK_PERIC0_USI00_BLK_CMU, "USI00", 0, 0, NULL),
	VCLK(USI01, VCLK_SPL_CLK_PERIC0_USI01_BLK_CMU, "USI01", 0, 0, NULL),
	VCLK(USI02, VCLK_SPL_CLK_PERIC0_USI02_BLK_CMU, "USI02", 0, 0, NULL),
	VCLK(USI03, VCLK_SPL_CLK_PERIC0_USI03_BLK_CMU, "USI03", 0, 0, NULL),
};

struct init_vclk exynos8895_peric1_vclks[] __initdata = {
	VCLK(SPI_CAM0, VCLK_SPL_CLK_PERIC1_SPI_CAM0_BLK_CMU, "SPI_CAM0", 0, 0, NULL),
	VCLK(SPI_CAM1, VCLK_SPL_CLK_PERIC1_SPI_CAM1_BLK_CMU, "SPI_CAM1", 0, 0, NULL),
	VCLK(UART_BT, VCLK_SPL_CLK_PERIC1_UART_BT_BLK_CMU, "UART_BT", 0, 0, NULL),
	VCLK(USI04, VCLK_SPL_CLK_PERIC1_USI04_BLK_CMU, "USI04", 0, 0, NULL),
	VCLK(USI05, VCLK_SPL_CLK_PERIC1_USI05_BLK_CMU, "USI05", 0, 0, NULL),
	VCLK(USI06, VCLK_SPL_CLK_PERIC1_USI06_BLK_CMU, "USI06", 0, 0, NULL),
	VCLK(USI07, VCLK_SPL_CLK_PERIC1_USI07_BLK_CMU, "USI07", 0, 0, NULL),
	VCLK(USI08, VCLK_SPL_CLK_PERIC1_USI08_BLK_CMU, "USI08", 0, 0, NULL),
	VCLK(USI09, VCLK_SPL_CLK_PERIC1_USI09_BLK_CMU, "USI09", 0, 0, NULL),
	VCLK(USI10, VCLK_SPL_CLK_PERIC1_USI10_BLK_CMU, "USI10", 0, 0, NULL),
	VCLK(USI11, VCLK_SPL_CLK_PERIC1_USI11_BLK_CMU, "USI11", 0, 0, NULL),
	VCLK(USI12, VCLK_SPL_CLK_PERIC1_USI12_BLK_CMU, "USI12", 0, 0, NULL),
	VCLK(USI13, VCLK_SPL_CLK_PERIC1_USI13_BLK_CMU, "USI13", 0, 0, NULL),
	VCLK(DOUT_CLKCMU_PERIC1_SPI_CAM0, CLKCMU_PERIC1_SPI_CAM0, "DOUT_CLKCMU_PERIC1_SPI_CAM0", 0, 0, NULL),
	VCLK(DOUT_CLKCMU_PERIC1_SPI_CAM1, CLKCMU_PERIC1_SPI_CAM1, "DOUT_CLKCMU_PERIC1_SPI_CAM1", 0, 0, NULL),
};

struct init_vclk exynos8895_cmu_vclks[] __initdata = {
	VCLK(CMU_CMUREF, VCLK_OCC_CMU_CMUREF_BLK_CMU, "CMU_CMUREF", 0, 0, NULL),
	VCLK(HPM, VCLK_CLKCMU_HPM_BLK_CMU, "HPM", 0, 0, NULL),
	VCLK(CIS_CLK0, VCLK_CLKCMU_CIS_CLK0_BLK_CMU, "CIS_CLK0", 0, 0, NULL),
	VCLK(CIS_CLK1, VCLK_CLKCMU_CIS_CLK1_BLK_CMU, "CIS_CLK1", 0, 0, NULL),
	VCLK(CIS_CLK2, VCLK_CLKCMU_CIS_CLK2_BLK_CMU, "CIS_CLK2", 0, 0, NULL),
	VCLK(CIS_CLK3, VCLK_CLKCMU_CIS_CLK3_BLK_CMU, "CIS_CLK3", 0, 0, NULL),
};

struct init_vclk exynos8895_dpu1_vclks[] __initdata = {
	VCLK(DECON2, VCLK_SPL_CLK_DPU1_DECON2_BLK_DPU1, "DECON2", 0, 0, NULL),
};

struct init_vclk exynos8895_vts_vclks[] __initdata = {
	VCLK(DMIC, VCLK_DIV_CLK_VTS_DMIC_BLK_VTS, "DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_DMICIF, DIV_CLK_VTS_DMICIF, "DOUT_CLK_VTS_DMICIF", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC, "DOUT_CLK_VTS_DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_DIV2, "DOUT_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
};

struct init_vclk exynos8895_dvfs_vclks[] __initdata = {
#if 0
	VCLK(DVFS_MIF, VCLK_VDD_MIF, "dvfs_mif", 0, VCLK_DFS, NULL),
	VCLK(DVFS_G3D, VCLK_VDD_G3D, "dvfs_g3d", 0, VCLK_DFS, NULL),
	VCLK(DVFS_BIG, VCLK_VDD_MNGS, "dvfs_big", 0, VCLK_DFS, NULL),
	VCLK(DVFS_LITTLE, VCLK_VDD_APOLLO, "dvfs_little", 0, VCLK_DFS, NULL),
	VCLK(DVFS_INT, VCLK_VDDI, "dvfs_int", 0, VCLK_DFS, NULL),
#endif
	VCLK(DFS_ABOX, VCLK_DFS_ABOX, "dfs_abox", 0, VCLK_DFS, NULL),
};

static __initdata struct of_device_id ext_clk_match[] = {
	{.compatible = "samsung,exynos8895-oscclk", .data = (void *)0},
	{},
};

void exynos8895_vclk_init(void)
{
	/* Common clock init */
	cal_clk_setrate(VCLK_BLK_BUS1, 266500);
	cal_clk_setrate(VCLK_BLK_BUSC, 266500);
	cal_clk_setrate(VCLK_BLK_CORE, 355333);
	cal_clk_setrate(VCLK_BLK_ABOX, 1179648);
	cal_clk_setrate(VCLK_BLK_CAM, 266500);
	cal_clk_setrate(VCLK_BLK_DBG, 200000);
	cal_clk_setrate(VCLK_BLK_DCAM, 222444);
	cal_clk_setrate(VCLK_BLK_DPU0, 157500);
	cal_clk_setrate(VCLK_BLK_DSP, 266500);
	cal_clk_setrate(VCLK_BLK_G2D, 266500);
	cal_clk_setrate(VCLK_BLK_ISPHQ, 266500);
	cal_clk_setrate(VCLK_BLK_ISPLP, 266500);
	cal_clk_setrate(VCLK_BLK_IVA, 266500);
	cal_clk_setrate(VCLK_BLK_MFC, 166833);
	cal_clk_setrate(VCLK_BLK_SRDZ, 266500);
	cal_clk_setrate(VCLK_BLK_VPU, 266500);
	cal_clk_setrate(VCLK_BLK_VTS, 49152);
}

/* register exynos8895 clocks */
void __init exynos8895_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	int ret;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	} else {
		panic("%s: unable to determine soc\n", __func__);
	}

	ret = cal_if_init(np);
	if (ret)
		panic("%s: unable to initialize cal-if\n", __func__);

	exynos8895_clk_privider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!exynos8895_clk_privider)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_register_of_fixed_ext(exynos8895_clk_privider, exynos8895_fixed_rate_ext_clks,
					  ARRAY_SIZE(exynos8895_fixed_rate_ext_clks),
					  ext_clk_match);
	/* register HWACG vclk */
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_abox_hwacg_vclks, ARRAY_SIZE(exynos8895_abox_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_apm_hwacg_vclks, ARRAY_SIZE(exynos8895_apm_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_bus1_hwacg_vclks, ARRAY_SIZE(exynos8895_bus1_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_busc_hwacg_vclks, ARRAY_SIZE(exynos8895_busc_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_cam_hwacg_vclks, ARRAY_SIZE(exynos8895_cam_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_cmu_hwacg_vclks, ARRAY_SIZE(exynos8895_cmu_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dcam_hwacg_vclks, ARRAY_SIZE(exynos8895_dcam_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dpu0_hwacg_vclks, ARRAY_SIZE(exynos8895_dpu0_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dpu1_hwacg_vclks, ARRAY_SIZE(exynos8895_dpu1_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dsp_hwacg_vclks, ARRAY_SIZE(exynos8895_dsp_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_fsys0_hwacg_vclks, ARRAY_SIZE(exynos8895_fsys0_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_fsys1_hwacg_vclks, ARRAY_SIZE(exynos8895_fsys1_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_g2d_hwacg_vclks, ARRAY_SIZE(exynos8895_g2d_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_g3d_hwacg_vclks, ARRAY_SIZE(exynos8895_g3d_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_imem_hwacg_vclks, ARRAY_SIZE(exynos8895_imem_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_isphq_hwacg_vclks, ARRAY_SIZE(exynos8895_isphq_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_isplq_hwacg_vclks, ARRAY_SIZE(exynos8895_isplq_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_iva_hwacg_vclks, ARRAY_SIZE(exynos8895_iva_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_mfc_hwacg_vclks, ARRAY_SIZE(exynos8895_mfc_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_peric0_hwacg_vclks, ARRAY_SIZE(exynos8895_peric0_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_peric1_hwacg_vclks, ARRAY_SIZE(exynos8895_peric1_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_peris_hwacg_vclks, ARRAY_SIZE(exynos8895_peris_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_srdz_hwacg_vclks, ARRAY_SIZE(exynos8895_srdz_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_vpu_hwacg_vclks, ARRAY_SIZE(exynos8895_vpu_hwacg_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_vts_hwacg_vclks, ARRAY_SIZE(exynos8895_vts_hwacg_vclks));

	/* register special vclk */
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_cmu_vclks, ARRAY_SIZE(exynos8895_cmu_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_abox_vclks, ARRAY_SIZE(exynos8895_abox_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_fsys0_vclks, ARRAY_SIZE(exynos8895_fsys0_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_fsys1_vclks, ARRAY_SIZE(exynos8895_fsys1_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_peric0_vclks, ARRAY_SIZE(exynos8895_peric0_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_peric1_vclks, ARRAY_SIZE(exynos8895_peric1_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dpu1_vclks, ARRAY_SIZE(exynos8895_dpu1_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_vts_vclks, ARRAY_SIZE(exynos8895_vts_vclks));
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_clkout_vclks, ARRAY_SIZE(exynos8895_clkout_vclks));

	/* register DVFS vclk */
	samsung_register_vclk(exynos8895_clk_privider, exynos8895_dvfs_vclks, ARRAY_SIZE(exynos8895_dvfs_vclks));

	clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll",CLK_SET_RATE_PARENT, 1, 1);

	samsung_clk_of_add_provider(np, exynos8895_clk_privider);

	late_time_init = exynos8895_vclk_init;

	pr_info("EXYNOS8895: Clock setup completed\n");
}

CLK_OF_DECLARE(exynos8895_clk, "samsung,exynos8895-clock", exynos8895_clk_init);