tree e568482e3fd178211e3caa00f9cb4d64ae31a804
parent 200276e6730c2817a77cfa6fc7e39ab3a63c4646
author Manuel Lauss <manuel.lauss@gmail.com> 1424253716 +0100
committer Ralf Baechle <ralf@linux-mips.org> 1424433702 +0100

MIPS: Alchemy: Fix cpu clock calculation

The current code uses bits 0-6 of the sys_cpupll register to calculate
core clock speed.  However this is only valid on Au1300, on all earlier
models the hardware only uses bits 0-5 to generate core clock.

This fixes clock calculation on the MTX1 (Au1500), where bit 6 of cpupll
is set as well, which ultimately lead the code to calculate a bogus cpu
core clock and also uart base clock down the line.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Reported-by: John Crispin <blogic@openwrt.org>
Tested-by: Bruno Randolf <br1@einfach.org>
Cc: stable@vger.kernel.org	[v3.17+]
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/9279/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>