Carolyn Wyborny | e52c0f9 | 2014-04-11 01:46:06 +0000 | [diff] [blame] | 1 | /* Intel(R) Gigabit Ethernet Linux driver |
| 2 | * Copyright(c) 2007-2014 Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program; if not, see <http://www.gnu.org/licenses/>. |
| 15 | * |
| 16 | * The full GNU General Public License is included in this distribution in |
| 17 | * the file called "COPYING". |
| 18 | * |
| 19 | * Contact Information: |
| 20 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 21 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 22 | */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 23 | |
| 24 | /* Linux PRO/1000 Ethernet Driver main header file */ |
| 25 | |
| 26 | #ifndef _IGB_H_ |
| 27 | #define _IGB_H_ |
| 28 | |
| 29 | #include "e1000_mac.h" |
| 30 | #include "e1000_82575.h" |
| 31 | |
Richard Cochran | 74d23cc | 2014-12-21 19:46:56 +0100 | [diff] [blame] | 32 | #include <linux/timecounter.h> |
Patrick Ohly | 33af6bc | 2009-02-12 05:03:43 +0000 | [diff] [blame] | 33 | #include <linux/net_tstamp.h> |
Richard Cochran | d339b13 | 2012-03-16 10:55:32 +0000 | [diff] [blame] | 34 | #include <linux/ptp_clock_kernel.h> |
Jiri Pirko | b2cb09b | 2011-07-21 03:27:27 +0000 | [diff] [blame] | 35 | #include <linux/bitops.h> |
| 36 | #include <linux/if_vlan.h> |
Carolyn Wyborny | 441fc6f | 2012-12-07 03:00:30 +0000 | [diff] [blame] | 37 | #include <linux/i2c.h> |
| 38 | #include <linux/i2c-algo-bit.h> |
Carolyn Wyborny | cd14ef5 | 2013-12-10 07:58:34 +0000 | [diff] [blame] | 39 | #include <linux/pci.h> |
Carolyn Wyborny | f4c01e9 | 2014-03-12 03:58:22 +0000 | [diff] [blame] | 40 | #include <linux/mdio.h> |
Patrick Ohly | 38c845c | 2009-02-12 05:03:41 +0000 | [diff] [blame] | 41 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 42 | struct igb_adapter; |
| 43 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 44 | #define E1000_PCS_CFG_IGN_SD 1 |
Carolyn Wyborny | 3860a0b | 2012-11-22 02:49:22 +0000 | [diff] [blame] | 45 | |
Alexander Duyck | 0ba8299 | 2011-08-26 07:45:47 +0000 | [diff] [blame] | 46 | /* Interrupt defines */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 47 | #define IGB_START_ITR 648 /* ~6000 ints/sec */ |
| 48 | #define IGB_4K_ITR 980 |
| 49 | #define IGB_20K_ITR 196 |
| 50 | #define IGB_70K_ITR 56 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 51 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 52 | /* TX/RX descriptor defines */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 53 | #define IGB_DEFAULT_TXD 256 |
| 54 | #define IGB_DEFAULT_TX_WORK 128 |
| 55 | #define IGB_MIN_TXD 80 |
| 56 | #define IGB_MAX_TXD 4096 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 57 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 58 | #define IGB_DEFAULT_RXD 256 |
| 59 | #define IGB_MIN_RXD 80 |
| 60 | #define IGB_MAX_RXD 4096 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 61 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 62 | #define IGB_DEFAULT_ITR 3 /* dynamic */ |
| 63 | #define IGB_MAX_ITR_USECS 10000 |
| 64 | #define IGB_MIN_ITR_USECS 10 |
| 65 | #define NON_Q_VECTORS 1 |
| 66 | #define MAX_Q_VECTORS 8 |
Carolyn Wyborny | cd14ef5 | 2013-12-10 07:58:34 +0000 | [diff] [blame] | 67 | #define MAX_MSIX_ENTRIES 10 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 68 | |
| 69 | /* Transmit and receive queues */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 70 | #define IGB_MAX_RX_QUEUES 8 |
| 71 | #define IGB_MAX_RX_QUEUES_82575 4 |
| 72 | #define IGB_MAX_RX_QUEUES_I211 2 |
| 73 | #define IGB_MAX_TX_QUEUES 8 |
| 74 | #define IGB_MAX_VF_MC_ENTRIES 30 |
| 75 | #define IGB_MAX_VF_FUNCTIONS 8 |
| 76 | #define IGB_MAX_VFTA_ENTRIES 128 |
| 77 | #define IGB_82576_VF_DEV_ID 0x10CA |
| 78 | #define IGB_I350_VF_DEV_ID 0x1520 |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 79 | |
Carolyn Wyborny | d67974f | 2012-06-14 16:04:19 +0000 | [diff] [blame] | 80 | /* NVM version defines */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 81 | #define IGB_MAJOR_MASK 0xF000 |
| 82 | #define IGB_MINOR_MASK 0x0FF0 |
| 83 | #define IGB_BUILD_MASK 0x000F |
| 84 | #define IGB_COMB_VER_MASK 0x00FF |
| 85 | #define IGB_MAJOR_SHIFT 12 |
| 86 | #define IGB_MINOR_SHIFT 4 |
| 87 | #define IGB_COMB_VER_SHFT 8 |
| 88 | #define IGB_NVM_VER_INVALID 0xFFFF |
| 89 | #define IGB_ETRACK_SHIFT 16 |
| 90 | #define NVM_ETRACK_WORD 0x0042 |
| 91 | #define NVM_COMB_VER_OFF 0x0083 |
| 92 | #define NVM_COMB_VER_PTR 0x003d |
Carolyn Wyborny | d67974f | 2012-06-14 16:04:19 +0000 | [diff] [blame] | 93 | |
Nathan Sullivan | 3f544d2 | 2016-05-03 18:10:56 -0500 | [diff] [blame] | 94 | /* Transmit and receive latency (for PTP timestamps) */ |
| 95 | #define IGB_I210_TX_LATENCY_10 9542 |
| 96 | #define IGB_I210_TX_LATENCY_100 1024 |
| 97 | #define IGB_I210_TX_LATENCY_1000 178 |
| 98 | #define IGB_I210_RX_LATENCY_10 20662 |
| 99 | #define IGB_I210_RX_LATENCY_100 2213 |
| 100 | #define IGB_I210_RX_LATENCY_1000 448 |
| 101 | |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 102 | struct vf_data_storage { |
| 103 | unsigned char vf_mac_addresses[ETH_ALEN]; |
| 104 | u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; |
| 105 | u16 num_vf_mc_hashes; |
Alexander Duyck | f2ca0db | 2009-10-27 23:46:57 +0000 | [diff] [blame] | 106 | u32 flags; |
| 107 | unsigned long last_nack; |
Williams, Mitch A | 8151d29 | 2010-02-10 01:44:24 +0000 | [diff] [blame] | 108 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
| 109 | u16 pf_qos; |
Lior Levy | 17dc566 | 2011-02-08 02:28:46 +0000 | [diff] [blame] | 110 | u16 tx_rate; |
Lior Levy | 70ea478 | 2013-03-03 20:27:48 +0000 | [diff] [blame] | 111 | bool spoofchk_enabled; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 112 | }; |
| 113 | |
Yury Kylulin | 4827cc3 | 2017-03-07 11:20:26 +0300 | [diff] [blame] | 114 | /* Number of unicast MAC filters reserved for the PF in the RAR registers */ |
| 115 | #define IGB_PF_MAC_FILTERS_RESERVED 3 |
| 116 | |
| 117 | struct vf_mac_filter { |
| 118 | struct list_head l; |
| 119 | int vf; |
| 120 | bool free; |
| 121 | u8 vf_mac[ETH_ALEN]; |
| 122 | }; |
| 123 | |
Alexander Duyck | f2ca0db | 2009-10-27 23:46:57 +0000 | [diff] [blame] | 124 | #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ |
Alexander Duyck | 7d5753f | 2009-10-27 23:47:16 +0000 | [diff] [blame] | 125 | #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ |
| 126 | #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ |
Williams, Mitch A | 8151d29 | 2010-02-10 01:44:24 +0000 | [diff] [blame] | 127 | #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ |
Alexander Duyck | f2ca0db | 2009-10-27 23:46:57 +0000 | [diff] [blame] | 128 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 129 | /* RX descriptor control thresholds. |
| 130 | * PTHRESH - MAC will consider prefetch if it has fewer than this number of |
| 131 | * descriptors available in its onboard memory. |
| 132 | * Setting this to 0 disables RX descriptor prefetch. |
| 133 | * HTHRESH - MAC will only prefetch if there are at least this many descriptors |
| 134 | * available in host memory. |
| 135 | * If PTHRESH is 0, this should also be 0. |
| 136 | * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back |
| 137 | * descriptors until either it has this many to write back, or the |
| 138 | * ITR timer expires. |
| 139 | */ |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 140 | #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 141 | #define IGB_RX_HTHRESH 8 |
Carolyn Wyborny | ceb5f13 | 2013-04-18 22:21:30 +0000 | [diff] [blame] | 142 | #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 143 | #define IGB_TX_HTHRESH 1 |
| 144 | #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
Carolyn Wyborny | cd14ef5 | 2013-12-10 07:58:34 +0000 | [diff] [blame] | 145 | (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 146 | #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ |
Carolyn Wyborny | cd14ef5 | 2013-12-10 07:58:34 +0000 | [diff] [blame] | 147 | (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 148 | |
| 149 | /* this is the size past which hardware will drop packets when setting LPE=0 */ |
| 150 | #define MAXIMUM_ETHERNET_VLAN_SIZE 1522 |
| 151 | |
| 152 | /* Supported Rx Buffer Sizes */ |
Alexander Duyck | de78d1f | 2012-09-25 00:31:12 +0000 | [diff] [blame] | 153 | #define IGB_RXBUFFER_256 256 |
| 154 | #define IGB_RXBUFFER_2048 2048 |
Alexander Duyck | 8649aae | 2017-02-06 18:27:03 -0800 | [diff] [blame] | 155 | #define IGB_RXBUFFER_3072 3072 |
Alexander Duyck | de78d1f | 2012-09-25 00:31:12 +0000 | [diff] [blame] | 156 | #define IGB_RX_HDR_LEN IGB_RXBUFFER_256 |
Alexander Duyck | cfbc871 | 2017-02-06 18:26:15 -0800 | [diff] [blame] | 157 | #define IGB_TS_HDR_LEN 16 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 158 | |
Alexander Duyck | cfbc871 | 2017-02-06 18:26:15 -0800 | [diff] [blame] | 159 | #define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) |
| 160 | #if (PAGE_SIZE < 8192) |
| 161 | #define IGB_MAX_FRAME_BUILD_SKB \ |
| 162 | (SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN) |
| 163 | #else |
| 164 | #define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN) |
| 165 | #endif |
| 166 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 167 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 168 | #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 169 | |
Alexander Duyck | 7bd1759 | 2017-02-06 18:25:26 -0800 | [diff] [blame] | 170 | #define IGB_RX_DMA_ATTR \ |
| 171 | (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) |
| 172 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 173 | #define AUTO_ALL_MODES 0 |
| 174 | #define IGB_EEPROM_APME 0x0400 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 175 | |
| 176 | #ifndef IGB_MASTER_SLAVE |
| 177 | /* Switch to override PHY master/slave setting */ |
| 178 | #define IGB_MASTER_SLAVE e1000_ms_hw_default |
| 179 | #endif |
| 180 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 181 | #define IGB_MNG_VLAN_NONE -1 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 182 | |
Alexander Duyck | 1d9daf4 | 2012-11-13 04:03:23 +0000 | [diff] [blame] | 183 | enum igb_tx_flags { |
| 184 | /* cmd_type flags */ |
| 185 | IGB_TX_FLAGS_VLAN = 0x01, |
| 186 | IGB_TX_FLAGS_TSO = 0x02, |
| 187 | IGB_TX_FLAGS_TSTAMP = 0x04, |
| 188 | |
| 189 | /* olinfo flags */ |
| 190 | IGB_TX_FLAGS_IPV4 = 0x10, |
| 191 | IGB_TX_FLAGS_CSUM = 0x20, |
| 192 | }; |
| 193 | |
| 194 | /* VLAN info */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 195 | #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 |
Alexander Duyck | 2bbfebe | 2011-08-26 07:44:59 +0000 | [diff] [blame] | 196 | #define IGB_TX_FLAGS_VLAN_SHIFT 16 |
| 197 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 198 | /* The largest size we can write to the descriptor is 65535. In order to |
Alexander Duyck | 21ba6fe | 2013-02-09 04:27:48 +0000 | [diff] [blame] | 199 | * maintain a power of two alignment we have to limit ourselves to 32K. |
| 200 | */ |
| 201 | #define IGB_MAX_TXD_PWR 15 |
Jacob Keller | a51d8c2 | 2016-04-13 16:08:28 -0700 | [diff] [blame] | 202 | #define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR) |
Alexander Duyck | 21ba6fe | 2013-02-09 04:27:48 +0000 | [diff] [blame] | 203 | |
| 204 | /* Tx Descriptors needed, worst case */ |
| 205 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD) |
| 206 | #define DESC_NEEDED (MAX_SKB_FRAGS + 4) |
| 207 | |
Akeem G. Abodunrin | f69aa39 | 2013-04-11 06:36:35 +0000 | [diff] [blame] | 208 | /* EEPROM byte offsets */ |
| 209 | #define IGB_SFF_8472_SWAP 0x5C |
| 210 | #define IGB_SFF_8472_COMP 0x5E |
| 211 | |
| 212 | /* Bitmasks */ |
| 213 | #define IGB_SFF_ADDRESSING_MODE 0x4 |
| 214 | #define IGB_SFF_8472_UNSUP 0x00 |
| 215 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 216 | /* wrapper around a pointer to a socket buffer, |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 217 | * so a DMA handle can be stored along with the buffer |
| 218 | */ |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 219 | struct igb_tx_buffer { |
Alexander Duyck | 8542db0 | 2011-08-26 07:44:43 +0000 | [diff] [blame] | 220 | union e1000_adv_tx_desc *next_to_watch; |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 221 | unsigned long time_stamp; |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 222 | struct sk_buff *skb; |
| 223 | unsigned int bytecount; |
| 224 | u16 gso_segs; |
Alexander Duyck | 7af40ad9 | 2011-08-26 07:45:15 +0000 | [diff] [blame] | 225 | __be16 protocol; |
Carolyn Wyborny | 9005df3 | 2014-04-11 01:45:34 +0000 | [diff] [blame] | 226 | |
Alexander Duyck | c9f14bf3 | 2012-09-18 01:56:27 +0000 | [diff] [blame] | 227 | DEFINE_DMA_UNMAP_ADDR(dma); |
| 228 | DEFINE_DMA_UNMAP_LEN(len); |
Alexander Duyck | ebe42d1 | 2011-08-26 07:45:09 +0000 | [diff] [blame] | 229 | u32 tx_flags; |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | struct igb_rx_buffer { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 233 | dma_addr_t dma; |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 234 | struct page *page; |
Alexander Duyck | bd4171a | 2016-12-14 15:05:34 -0800 | [diff] [blame] | 235 | #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) |
| 236 | __u32 page_offset; |
| 237 | #else |
| 238 | __u16 page_offset; |
| 239 | #endif |
| 240 | __u16 pagecnt_bias; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 241 | }; |
| 242 | |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 243 | struct igb_tx_queue_stats { |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 244 | u64 packets; |
| 245 | u64 bytes; |
Alexander Duyck | 04a5fcaa | 2009-10-27 15:52:27 +0000 | [diff] [blame] | 246 | u64 restart_queue; |
Eric Dumazet | 12dcd86 | 2010-10-15 17:27:10 +0000 | [diff] [blame] | 247 | u64 restart_queue2; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 248 | }; |
| 249 | |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 250 | struct igb_rx_queue_stats { |
| 251 | u64 packets; |
| 252 | u64 bytes; |
| 253 | u64 drops; |
Alexander Duyck | 04a5fcaa | 2009-10-27 15:52:27 +0000 | [diff] [blame] | 254 | u64 csum_err; |
| 255 | u64 alloc_failed; |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 256 | }; |
| 257 | |
Alexander Duyck | 0ba8299 | 2011-08-26 07:45:47 +0000 | [diff] [blame] | 258 | struct igb_ring_container { |
| 259 | struct igb_ring *ring; /* pointer to linked list of rings */ |
| 260 | unsigned int total_bytes; /* total bytes processed this int */ |
| 261 | unsigned int total_packets; /* total packets processed this int */ |
| 262 | u16 work_limit; /* total work allowed per interrupt */ |
| 263 | u8 count; /* total number of rings in vector */ |
| 264 | u8 itr; /* current ITR setting for ring */ |
| 265 | }; |
| 266 | |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 267 | struct igb_ring { |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 268 | struct igb_q_vector *q_vector; /* backlink to q_vector */ |
| 269 | struct net_device *netdev; /* back pointer to net_device */ |
| 270 | struct device *dev; /* device pointer for dma mapping */ |
Alexander Duyck | 0603464 | 2011-08-26 07:44:22 +0000 | [diff] [blame] | 271 | union { /* array of buffer info structs */ |
| 272 | struct igb_tx_buffer *tx_buffer_info; |
| 273 | struct igb_rx_buffer *rx_buffer_info; |
| 274 | }; |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 275 | void *desc; /* descriptor ring memory */ |
| 276 | unsigned long flags; /* ring specific flags */ |
| 277 | void __iomem *tail; /* pointer to ring tail register */ |
Alexander Duyck | 5536d21 | 2012-09-25 00:31:17 +0000 | [diff] [blame] | 278 | dma_addr_t dma; /* phys address of the ring */ |
| 279 | unsigned int size; /* length of desc. ring in bytes */ |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 280 | |
| 281 | u16 count; /* number of desc. in the ring */ |
| 282 | u8 queue_index; /* logical index of the ring*/ |
| 283 | u8 reg_idx; /* physical index of the ring */ |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 284 | |
| 285 | /* everything past this point are written often */ |
Alexander Duyck | 5536d21 | 2012-09-25 00:31:17 +0000 | [diff] [blame] | 286 | u16 next_to_clean; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 287 | u16 next_to_use; |
Alexander Duyck | cbc8e55 | 2012-09-25 00:31:02 +0000 | [diff] [blame] | 288 | u16 next_to_alloc; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 289 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 290 | union { |
| 291 | /* TX */ |
| 292 | struct { |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 293 | struct igb_tx_queue_stats tx_stats; |
Eric Dumazet | 12dcd86 | 2010-10-15 17:27:10 +0000 | [diff] [blame] | 294 | struct u64_stats_sync tx_syncp; |
| 295 | struct u64_stats_sync tx_syncp2; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 296 | }; |
| 297 | /* RX */ |
| 298 | struct { |
Alexander Duyck | 1a1c225 | 2012-09-25 00:30:52 +0000 | [diff] [blame] | 299 | struct sk_buff *skb; |
Jesper Dangaard Brouer | 8c0ab70 | 2009-05-26 13:50:31 +0000 | [diff] [blame] | 300 | struct igb_rx_queue_stats rx_stats; |
Eric Dumazet | 12dcd86 | 2010-10-15 17:27:10 +0000 | [diff] [blame] | 301 | struct u64_stats_sync rx_syncp; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 302 | }; |
| 303 | }; |
Alexander Duyck | 5536d21 | 2012-09-25 00:31:17 +0000 | [diff] [blame] | 304 | } ____cacheline_internodealigned_in_smp; |
| 305 | |
| 306 | struct igb_q_vector { |
| 307 | struct igb_adapter *adapter; /* backlink */ |
| 308 | int cpu; /* CPU for DCA */ |
| 309 | u32 eims_value; /* EIMS mask value */ |
| 310 | |
| 311 | u16 itr_val; |
| 312 | u8 set_itr; |
| 313 | void __iomem *itr_register; |
| 314 | |
| 315 | struct igb_ring_container rx, tx; |
| 316 | |
| 317 | struct napi_struct napi; |
| 318 | struct rcu_head rcu; /* to avoid race with update stats on free */ |
| 319 | char name[IFNAMSIZ + 9]; |
| 320 | |
| 321 | /* for dynamic allocation of rings associated with this q_vector */ |
| 322 | struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 323 | }; |
| 324 | |
Alexander Duyck | 866cff0 | 2011-08-26 07:45:36 +0000 | [diff] [blame] | 325 | enum e1000_ring_flags_t { |
Alexander Duyck | 8649aae | 2017-02-06 18:27:03 -0800 | [diff] [blame] | 326 | IGB_RING_FLAG_RX_3K_BUFFER, |
Alexander Duyck | e3cdf68 | 2017-02-06 18:27:14 -0800 | [diff] [blame] | 327 | IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, |
Alexander Duyck | 866cff0 | 2011-08-26 07:45:36 +0000 | [diff] [blame] | 328 | IGB_RING_FLAG_RX_SCTP_CSUM, |
Alexander Duyck | 8be10e9 | 2011-08-26 07:47:11 +0000 | [diff] [blame] | 329 | IGB_RING_FLAG_RX_LB_VLAN_BSWAP, |
Alexander Duyck | 866cff0 | 2011-08-26 07:45:36 +0000 | [diff] [blame] | 330 | IGB_RING_FLAG_TX_CTX_IDX, |
| 331 | IGB_RING_FLAG_TX_DETECT_HANG |
| 332 | }; |
Alexander Duyck | 85ad76b | 2009-10-27 15:52:46 +0000 | [diff] [blame] | 333 | |
Alexander Duyck | 8649aae | 2017-02-06 18:27:03 -0800 | [diff] [blame] | 334 | #define ring_uses_large_buffer(ring) \ |
| 335 | test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
| 336 | #define set_ring_uses_large_buffer(ring) \ |
| 337 | set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
| 338 | #define clear_ring_uses_large_buffer(ring) \ |
| 339 | clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) |
| 340 | |
Alexander Duyck | e3cdf68 | 2017-02-06 18:27:14 -0800 | [diff] [blame] | 341 | #define ring_uses_build_skb(ring) \ |
| 342 | test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) |
| 343 | #define set_ring_build_skb_enabled(ring) \ |
| 344 | set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) |
| 345 | #define clear_ring_build_skb_enabled(ring) \ |
| 346 | clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) |
| 347 | |
Alexander Duyck | 8649aae | 2017-02-06 18:27:03 -0800 | [diff] [blame] | 348 | static inline unsigned int igb_rx_bufsz(struct igb_ring *ring) |
| 349 | { |
| 350 | #if (PAGE_SIZE < 8192) |
| 351 | if (ring_uses_large_buffer(ring)) |
| 352 | return IGB_RXBUFFER_3072; |
Alexander Duyck | e3cdf68 | 2017-02-06 18:27:14 -0800 | [diff] [blame] | 353 | |
| 354 | if (ring_uses_build_skb(ring)) |
| 355 | return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN; |
Alexander Duyck | 8649aae | 2017-02-06 18:27:03 -0800 | [diff] [blame] | 356 | #endif |
| 357 | return IGB_RXBUFFER_2048; |
| 358 | } |
| 359 | |
| 360 | static inline unsigned int igb_rx_pg_order(struct igb_ring *ring) |
| 361 | { |
| 362 | #if (PAGE_SIZE < 8192) |
| 363 | if (ring_uses_large_buffer(ring)) |
| 364 | return 1; |
| 365 | #endif |
| 366 | return 0; |
| 367 | } |
| 368 | |
| 369 | #define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring)) |
| 370 | |
Alexander Duyck | e032afc | 2011-08-26 07:44:48 +0000 | [diff] [blame] | 371 | #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) |
Alexander Duyck | 85ad76b | 2009-10-27 15:52:46 +0000 | [diff] [blame] | 372 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 373 | #define IGB_RX_DESC(R, i) \ |
Alexander Duyck | 6013690 | 2011-08-26 07:44:05 +0000 | [diff] [blame] | 374 | (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 375 | #define IGB_TX_DESC(R, i) \ |
Alexander Duyck | 6013690 | 2011-08-26 07:44:05 +0000 | [diff] [blame] | 376 | (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 377 | #define IGB_TX_CTXTDESC(R, i) \ |
Alexander Duyck | 6013690 | 2011-08-26 07:44:05 +0000 | [diff] [blame] | 378 | (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 379 | |
Alexander Duyck | 3ceb90f | 2011-08-26 07:46:03 +0000 | [diff] [blame] | 380 | /* igb_test_staterr - tests bits within Rx descriptor status and error fields */ |
| 381 | static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, |
| 382 | const u32 stat_err_bits) |
| 383 | { |
| 384 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); |
| 385 | } |
| 386 | |
Alexander Duyck | d7ee5b3 | 2009-10-27 15:54:23 +0000 | [diff] [blame] | 387 | /* igb_desc_unused - calculate if we have unused descriptors */ |
| 388 | static inline int igb_desc_unused(struct igb_ring *ring) |
| 389 | { |
| 390 | if (ring->next_to_clean > ring->next_to_use) |
| 391 | return ring->next_to_clean - ring->next_to_use - 1; |
| 392 | |
| 393 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; |
| 394 | } |
| 395 | |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 396 | #ifdef CONFIG_IGB_HWMON |
| 397 | |
| 398 | #define IGB_HWMON_TYPE_LOC 0 |
| 399 | #define IGB_HWMON_TYPE_TEMP 1 |
| 400 | #define IGB_HWMON_TYPE_CAUTION 2 |
| 401 | #define IGB_HWMON_TYPE_MAX 3 |
| 402 | |
| 403 | struct hwmon_attr { |
| 404 | struct device_attribute dev_attr; |
| 405 | struct e1000_hw *hw; |
| 406 | struct e1000_thermal_diode_data *sensor; |
| 407 | char name[12]; |
| 408 | }; |
| 409 | |
| 410 | struct hwmon_buff { |
Guenter Roeck | e3670b8 | 2013-11-26 07:15:23 +0000 | [diff] [blame] | 411 | struct attribute_group group; |
| 412 | const struct attribute_group *groups[2]; |
| 413 | struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1]; |
| 414 | struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4]; |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 415 | unsigned int n_hwmon; |
| 416 | }; |
| 417 | #endif |
| 418 | |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 419 | /* The number of L2 ether-type filter registers, Index 3 is reserved |
| 420 | * for PTP 1588 timestamp |
| 421 | */ |
| 422 | #define MAX_ETYPE_FILTER (4 - 1) |
| 423 | /* ETQF filter list: one static filter per filter consumer. This is |
| 424 | * to avoid filter collisions later. Add new filters here!! |
| 425 | * |
| 426 | * Current filters: Filter 3 |
| 427 | */ |
| 428 | #define IGB_ETQF_FILTER_1588 3 |
| 429 | |
Richard Cochran | 720db4f | 2014-11-21 20:51:26 +0000 | [diff] [blame] | 430 | #define IGB_N_EXTTS 2 |
| 431 | #define IGB_N_PEROUT 2 |
| 432 | #define IGB_N_SDP 4 |
Laura Mihaela Vasilescu | c342b39 | 2013-07-31 20:19:48 +0000 | [diff] [blame] | 433 | #define IGB_RETA_SIZE 128 |
| 434 | |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 435 | enum igb_filter_match_flags { |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 436 | IGB_FILTER_FLAG_ETHER_TYPE = 0x1, |
Gangfeng Huang | 7a277a9 | 2016-07-06 13:22:56 +0800 | [diff] [blame] | 437 | IGB_FILTER_FLAG_VLAN_TCI = 0x2, |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | #define IGB_MAX_RXNFC_FILTERS 16 |
| 441 | |
| 442 | /* RX network flow classification data structure */ |
| 443 | struct igb_nfc_input { |
| 444 | /* Byte layout in order, all values with MSB first: |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 445 | * match_flags - 1 byte |
| 446 | * etype - 2 bytes |
Gangfeng Huang | 7a277a9 | 2016-07-06 13:22:56 +0800 | [diff] [blame] | 447 | * vlan_tci - 2 bytes |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 448 | */ |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 449 | u8 match_flags; |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 450 | __be16 etype; |
Gangfeng Huang | 7a277a9 | 2016-07-06 13:22:56 +0800 | [diff] [blame] | 451 | __be16 vlan_tci; |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 452 | }; |
| 453 | |
| 454 | struct igb_nfc_filter { |
| 455 | struct hlist_node nfc_node; |
| 456 | struct igb_nfc_input filter; |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 457 | u16 etype_reg_index; |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 458 | u16 sw_idx; |
| 459 | u16 action; |
| 460 | }; |
| 461 | |
Yury Kylulin | 83c2133 | 2017-03-07 11:20:25 +0300 | [diff] [blame] | 462 | struct igb_mac_addr { |
| 463 | u8 addr[ETH_ALEN]; |
| 464 | u8 queue; |
| 465 | u8 state; /* bitmask */ |
| 466 | }; |
| 467 | |
| 468 | #define IGB_MAC_STATE_DEFAULT 0x1 |
| 469 | #define IGB_MAC_STATE_IN_USE 0x2 |
| 470 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 471 | /* board specific private data structure */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 472 | struct igb_adapter { |
Jiri Pirko | b2cb09b | 2011-07-21 03:27:27 +0000 | [diff] [blame] | 473 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 474 | |
| 475 | struct net_device *netdev; |
| 476 | |
| 477 | unsigned long state; |
| 478 | unsigned int flags; |
| 479 | |
| 480 | unsigned int num_q_vectors; |
Carolyn Wyborny | cd14ef5 | 2013-12-10 07:58:34 +0000 | [diff] [blame] | 481 | struct msix_entry msix_entries[MAX_MSIX_ENTRIES]; |
Alexander Duyck | 2e5655e | 2009-10-27 23:50:38 +0000 | [diff] [blame] | 482 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 483 | /* Interrupt Throttle Rate */ |
Alexander Duyck | 4fc82ad | 2009-10-27 23:45:42 +0000 | [diff] [blame] | 484 | u32 rx_itr_setting; |
| 485 | u32 tx_itr_setting; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 486 | u16 tx_itr; |
| 487 | u16 rx_itr; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 488 | |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 489 | /* TX */ |
Alexander Duyck | 13fde97 | 2011-10-05 13:35:24 +0000 | [diff] [blame] | 490 | u16 tx_work_limit; |
Alexander Duyck | 238ac81 | 2011-08-26 07:43:48 +0000 | [diff] [blame] | 491 | u32 tx_timeout_count; |
| 492 | int num_tx_queues; |
| 493 | struct igb_ring *tx_ring[16]; |
| 494 | |
| 495 | /* RX */ |
| 496 | int num_rx_queues; |
| 497 | struct igb_ring *rx_ring[16]; |
| 498 | |
| 499 | u32 max_frame_size; |
| 500 | u32 min_frame_size; |
| 501 | |
| 502 | struct timer_list watchdog_timer; |
| 503 | struct timer_list phy_info_timer; |
| 504 | |
| 505 | u16 mng_vlan_id; |
| 506 | u32 bd_number; |
| 507 | u32 wol; |
| 508 | u32 en_mng_pt; |
| 509 | u16 link_speed; |
| 510 | u16 link_duplex; |
| 511 | |
Jarod Wilson | 73bf804 | 2015-09-10 15:37:50 -0400 | [diff] [blame] | 512 | u8 __iomem *io_addr; /* Mainly for iounmap use */ |
| 513 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 514 | struct work_struct reset_task; |
| 515 | struct work_struct watchdog_task; |
| 516 | bool fc_autoneg; |
| 517 | u8 tx_timeout_factor; |
| 518 | struct timer_list blink_timer; |
| 519 | unsigned long led_status; |
| 520 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 521 | /* OS defined structs */ |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 522 | struct pci_dev *pdev; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 523 | |
Eric Dumazet | 12dcd86 | 2010-10-15 17:27:10 +0000 | [diff] [blame] | 524 | spinlock_t stats64_lock; |
| 525 | struct rtnl_link_stats64 stats64; |
| 526 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 527 | /* structs defined in e1000_hw.h */ |
| 528 | struct e1000_hw hw; |
| 529 | struct e1000_hw_stats stats; |
| 530 | struct e1000_phy_info phy_info; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 531 | |
| 532 | u32 test_icr; |
| 533 | struct igb_ring test_tx_ring; |
| 534 | struct igb_ring test_rx_ring; |
| 535 | |
| 536 | int msg_enable; |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 537 | |
Alexander Duyck | 047e003 | 2009-10-27 15:49:27 +0000 | [diff] [blame] | 538 | struct igb_q_vector *q_vector[MAX_Q_VECTORS]; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 539 | u32 eims_enable_mask; |
PJ Waskiewicz | 844290e | 2008-06-27 11:00:39 -0700 | [diff] [blame] | 540 | u32 eims_other; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 541 | |
| 542 | /* to not mess up cache alignment, always add to the bottom */ |
Alexander Duyck | 2e5655e | 2009-10-27 23:50:38 +0000 | [diff] [blame] | 543 | u16 tx_ring_count; |
| 544 | u16 rx_ring_count; |
Alexander Duyck | 1bfaf07 | 2009-02-19 20:39:23 -0800 | [diff] [blame] | 545 | unsigned int vfs_allocated_count; |
Alexander Duyck | 4ae196d | 2009-02-19 20:40:07 -0800 | [diff] [blame] | 546 | struct vf_data_storage *vf_data; |
Lior Levy | 17dc566 | 2011-02-08 02:28:46 +0000 | [diff] [blame] | 547 | int vf_rate_link_speed; |
Alexander Duyck | a99955f | 2009-11-12 18:37:19 +0000 | [diff] [blame] | 548 | u32 rss_queues; |
Greg Rose | 1380046 | 2010-11-06 02:08:26 +0000 | [diff] [blame] | 549 | u32 wvbr; |
Carolyn Wyborny | 1128c75 | 2011-10-14 00:13:49 +0000 | [diff] [blame] | 550 | u32 *shadow_vfta; |
Richard Cochran | d339b13 | 2012-03-16 10:55:32 +0000 | [diff] [blame] | 551 | |
| 552 | struct ptp_clock *ptp_clock; |
Matthew Vick | a79f4f8 | 2012-08-10 05:40:44 +0000 | [diff] [blame] | 553 | struct ptp_clock_info ptp_caps; |
| 554 | struct delayed_work ptp_overflow_work; |
Matthew Vick | 1f6e817 | 2012-08-18 07:26:33 +0000 | [diff] [blame] | 555 | struct work_struct ptp_tx_work; |
| 556 | struct sk_buff *ptp_tx_skb; |
Jacob Keller | 6ab5f7b | 2014-01-11 07:20:06 +0000 | [diff] [blame] | 557 | struct hwtstamp_config tstamp_config; |
Matthew Vick | 428f1f7 | 2012-12-13 07:20:34 +0000 | [diff] [blame] | 558 | unsigned long ptp_tx_start; |
Matthew Vick | fc58075 | 2012-12-13 07:20:35 +0000 | [diff] [blame] | 559 | unsigned long last_rx_ptp_check; |
Jakub Kicinski | 5499a96 | 2014-04-02 10:33:33 +0000 | [diff] [blame] | 560 | unsigned long last_rx_timestamp; |
Jacob Keller | 462f118 | 2016-05-24 13:56:27 -0700 | [diff] [blame] | 561 | unsigned int ptp_flags; |
Richard Cochran | d339b13 | 2012-03-16 10:55:32 +0000 | [diff] [blame] | 562 | spinlock_t tmreg_lock; |
| 563 | struct cyclecounter cc; |
| 564 | struct timecounter tc; |
Matthew Vick | 428f1f7 | 2012-12-13 07:20:34 +0000 | [diff] [blame] | 565 | u32 tx_hwtstamp_timeouts; |
Matthew Vick | fc58075 | 2012-12-13 07:20:35 +0000 | [diff] [blame] | 566 | u32 rx_hwtstamp_cleared; |
Jacob Keller | ac28b41 | 2016-09-09 09:10:51 -0700 | [diff] [blame] | 567 | bool pps_sys_wrap_on; |
Matthew Vick | 3c89f6d | 2012-08-10 05:40:43 +0000 | [diff] [blame] | 568 | |
Richard Cochran | 720db4f | 2014-11-21 20:51:26 +0000 | [diff] [blame] | 569 | struct ptp_pin_desc sdp_config[IGB_N_SDP]; |
| 570 | struct { |
Arnd Bergmann | 40c9b07 | 2015-09-30 13:26:33 +0200 | [diff] [blame] | 571 | struct timespec64 start; |
| 572 | struct timespec64 period; |
Richard Cochran | 720db4f | 2014-11-21 20:51:26 +0000 | [diff] [blame] | 573 | } perout[IGB_N_PEROUT]; |
| 574 | |
Carolyn Wyborny | d67974f | 2012-06-14 16:04:19 +0000 | [diff] [blame] | 575 | char fw_version[32]; |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 576 | #ifdef CONFIG_IGB_HWMON |
Guenter Roeck | e3670b8 | 2013-11-26 07:15:23 +0000 | [diff] [blame] | 577 | struct hwmon_buff *igb_hwmon_buff; |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 578 | bool ets; |
| 579 | #endif |
Carolyn Wyborny | 441fc6f | 2012-12-07 03:00:30 +0000 | [diff] [blame] | 580 | struct i2c_algo_bit_data i2c_algo; |
| 581 | struct i2c_adapter i2c_adap; |
Carolyn Wyborny | 603e86f | 2013-02-20 07:40:55 +0000 | [diff] [blame] | 582 | struct i2c_client *i2c_client; |
Laura Mihaela Vasilescu | ed12cc9 | 2013-07-31 20:19:54 +0000 | [diff] [blame] | 583 | u32 rss_indir_tbl_init; |
| 584 | u8 rss_indir_tbl[IGB_RETA_SIZE]; |
Akeem G Abodunrin | aa9b8cc | 2013-08-28 02:22:43 +0000 | [diff] [blame] | 585 | |
| 586 | unsigned long link_check_timeout; |
Carolyn Wyborny | 56cec24 | 2013-10-17 05:36:26 +0000 | [diff] [blame] | 587 | int copper_tries; |
| 588 | struct e1000_info ei; |
Carolyn Wyborny | f4c01e9 | 2014-03-12 03:58:22 +0000 | [diff] [blame] | 589 | u16 eee_advert; |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 590 | |
| 591 | /* RX network flow classification support */ |
| 592 | struct hlist_head nfc_filter_list; |
| 593 | unsigned int nfc_filter_count; |
| 594 | /* lock for RX network flow classification filter */ |
| 595 | spinlock_t nfc_lock; |
Gangfeng Huang | 64c75d4 | 2016-07-06 13:22:55 +0800 | [diff] [blame] | 596 | bool etype_bitmap[MAX_ETYPE_FILTER]; |
Yury Kylulin | 83c2133 | 2017-03-07 11:20:25 +0300 | [diff] [blame] | 597 | |
| 598 | struct igb_mac_addr *mac_table; |
Yury Kylulin | 4827cc3 | 2017-03-07 11:20:26 +0300 | [diff] [blame] | 599 | struct vf_mac_filter vf_macs; |
| 600 | struct vf_mac_filter *vf_mac_list; |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 601 | }; |
| 602 | |
Jacob Keller | 462f118 | 2016-05-24 13:56:27 -0700 | [diff] [blame] | 603 | /* flags controlling PTP/1588 function */ |
| 604 | #define IGB_PTP_ENABLED BIT(0) |
Jacob Keller | 6373716 | 2016-05-24 13:56:28 -0700 | [diff] [blame] | 605 | #define IGB_PTP_OVERFLOW_CHECK BIT(1) |
Jacob Keller | 462f118 | 2016-05-24 13:56:27 -0700 | [diff] [blame] | 606 | |
Jacob Keller | a51d8c2 | 2016-04-13 16:08:28 -0700 | [diff] [blame] | 607 | #define IGB_FLAG_HAS_MSI BIT(0) |
| 608 | #define IGB_FLAG_DCA_ENABLED BIT(1) |
| 609 | #define IGB_FLAG_QUAD_PORT_A BIT(2) |
| 610 | #define IGB_FLAG_QUEUE_PAIRS BIT(3) |
| 611 | #define IGB_FLAG_DMAC BIT(4) |
Jacob Keller | a51d8c2 | 2016-04-13 16:08:28 -0700 | [diff] [blame] | 612 | #define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6) |
| 613 | #define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7) |
| 614 | #define IGB_FLAG_WOL_SUPPORTED BIT(8) |
| 615 | #define IGB_FLAG_NEED_LINK_UPDATE BIT(9) |
| 616 | #define IGB_FLAG_MEDIA_RESET BIT(10) |
| 617 | #define IGB_FLAG_MAS_CAPABLE BIT(11) |
| 618 | #define IGB_FLAG_MAS_ENABLE BIT(12) |
| 619 | #define IGB_FLAG_HAS_MSIX BIT(13) |
| 620 | #define IGB_FLAG_EEE BIT(14) |
Alexander Duyck | 16903ca | 2016-01-06 23:11:18 -0800 | [diff] [blame] | 621 | #define IGB_FLAG_VLAN_PROMISC BIT(15) |
Alexander Duyck | e089129 | 2017-02-06 18:26:52 -0800 | [diff] [blame] | 622 | #define IGB_FLAG_RX_LEGACY BIT(16) |
Carolyn Wyborny | 56cec24 | 2013-10-17 05:36:26 +0000 | [diff] [blame] | 623 | |
| 624 | /* Media Auto Sense */ |
| 625 | #define IGB_MAS_ENABLE_0 0X0001 |
| 626 | #define IGB_MAS_ENABLE_1 0X0002 |
| 627 | #define IGB_MAS_ENABLE_2 0X0004 |
| 628 | #define IGB_MAS_ENABLE_3 0X0008 |
Carolyn Wyborny | 831ec0b | 2011-03-11 20:43:54 -0800 | [diff] [blame] | 629 | |
| 630 | /* DMA Coalescing defines */ |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 631 | #define IGB_MIN_TXPBSIZE 20408 |
| 632 | #define IGB_TX_BUF_4096 4096 |
| 633 | #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ |
Alexander Duyck | 7dfc16f | 2008-07-08 15:10:46 -0700 | [diff] [blame] | 634 | |
Jeff Kirsher | b980ac1 | 2013-02-23 07:29:56 +0000 | [diff] [blame] | 635 | #define IGB_82576_TSYNC_SHIFT 19 |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 636 | enum e1000_state_t { |
| 637 | __IGB_TESTING, |
| 638 | __IGB_RESETTING, |
Jakub Kicinski | ed4420a | 2014-03-15 14:55:32 +0000 | [diff] [blame] | 639 | __IGB_DOWN, |
| 640 | __IGB_PTP_TX_IN_PROGRESS, |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 641 | }; |
| 642 | |
| 643 | enum igb_boards { |
| 644 | board_82575, |
| 645 | }; |
| 646 | |
| 647 | extern char igb_driver_name[]; |
| 648 | extern char igb_driver_version[]; |
| 649 | |
Stefan Assmann | 46eafa5 | 2016-02-03 09:20:50 +0100 | [diff] [blame] | 650 | int igb_open(struct net_device *netdev); |
| 651 | int igb_close(struct net_device *netdev); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 652 | int igb_up(struct igb_adapter *); |
| 653 | void igb_down(struct igb_adapter *); |
| 654 | void igb_reinit_locked(struct igb_adapter *); |
| 655 | void igb_reset(struct igb_adapter *); |
Laura Mihaela Vasilescu | 907b783 | 2013-10-01 04:33:56 -0700 | [diff] [blame] | 656 | int igb_reinit_queues(struct igb_adapter *); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 657 | void igb_write_rss_indir_tbl(struct igb_adapter *); |
| 658 | int igb_set_spd_dplx(struct igb_adapter *, u32, u8); |
| 659 | int igb_setup_tx_resources(struct igb_ring *); |
| 660 | int igb_setup_rx_resources(struct igb_ring *); |
| 661 | void igb_free_tx_resources(struct igb_ring *); |
| 662 | void igb_free_rx_resources(struct igb_ring *); |
| 663 | void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); |
| 664 | void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); |
| 665 | void igb_setup_tctl(struct igb_adapter *); |
| 666 | void igb_setup_rctl(struct igb_adapter *); |
| 667 | netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 668 | void igb_alloc_rx_buffers(struct igb_ring *, u16); |
| 669 | void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); |
| 670 | bool igb_has_link(struct igb_adapter *adapter); |
| 671 | void igb_set_ethtool_ops(struct net_device *); |
| 672 | void igb_power_up_link(struct igb_adapter *); |
| 673 | void igb_set_fw_version(struct igb_adapter *); |
| 674 | void igb_ptp_init(struct igb_adapter *adapter); |
| 675 | void igb_ptp_stop(struct igb_adapter *adapter); |
| 676 | void igb_ptp_reset(struct igb_adapter *adapter); |
Jacob Keller | e3f2350 | 2016-05-24 13:56:30 -0700 | [diff] [blame] | 677 | void igb_ptp_suspend(struct igb_adapter *adapter); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 678 | void igb_ptp_rx_hang(struct igb_adapter *adapter); |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 679 | void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb); |
Alexander Duyck | 3456fd5 | 2017-02-06 18:26:40 -0800 | [diff] [blame] | 680 | void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va, |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 681 | struct sk_buff *skb); |
Jacob Keller | 6ab5f7b | 2014-01-11 07:20:06 +0000 | [diff] [blame] | 682 | int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); |
| 683 | int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); |
Shota Suzuki | 72ddef0 | 2015-07-01 09:25:52 +0900 | [diff] [blame] | 684 | void igb_set_flag_queue_pairs(struct igb_adapter *, const u32); |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 685 | #ifdef CONFIG_IGB_HWMON |
Joe Perches | 5ccc921 | 2013-09-23 11:37:59 -0700 | [diff] [blame] | 686 | void igb_sysfs_exit(struct igb_adapter *adapter); |
| 687 | int igb_sysfs_init(struct igb_adapter *adapter); |
Carolyn Wyborny | e428893 | 2012-12-07 03:01:42 +0000 | [diff] [blame] | 688 | #endif |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 689 | static inline s32 igb_reset_phy(struct e1000_hw *hw) |
| 690 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 691 | if (hw->phy.ops.reset) |
| 692 | return hw->phy.ops.reset(hw); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 693 | |
| 694 | return 0; |
| 695 | } |
| 696 | |
| 697 | static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) |
| 698 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 699 | if (hw->phy.ops.read_reg) |
| 700 | return hw->phy.ops.read_reg(hw, offset, data); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 701 | |
| 702 | return 0; |
| 703 | } |
| 704 | |
| 705 | static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) |
| 706 | { |
Alexander Duyck | a8d2a0c | 2009-02-06 23:17:26 +0000 | [diff] [blame] | 707 | if (hw->phy.ops.write_reg) |
| 708 | return hw->phy.ops.write_reg(hw, offset, data); |
Alexander Duyck | f5f4cf0 | 2008-11-21 21:30:24 -0800 | [diff] [blame] | 709 | |
| 710 | return 0; |
| 711 | } |
| 712 | |
| 713 | static inline s32 igb_get_phy_info(struct e1000_hw *hw) |
| 714 | { |
| 715 | if (hw->phy.ops.get_phy_info) |
| 716 | return hw->phy.ops.get_phy_info(hw); |
| 717 | |
| 718 | return 0; |
| 719 | } |
| 720 | |
Eric Dumazet | bdbc063 | 2012-01-04 20:23:36 +0000 | [diff] [blame] | 721 | static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) |
| 722 | { |
| 723 | return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); |
| 724 | } |
| 725 | |
Gangfeng Huang | 0e71def | 2016-07-06 13:22:54 +0800 | [diff] [blame] | 726 | int igb_add_filter(struct igb_adapter *adapter, |
| 727 | struct igb_nfc_filter *input); |
| 728 | int igb_erase_filter(struct igb_adapter *adapter, |
| 729 | struct igb_nfc_filter *input); |
| 730 | |
Auke Kok | 9d5c824 | 2008-01-24 02:22:38 -0800 | [diff] [blame] | 731 | #endif /* _IGB_H_ */ |