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Carolyn Wybornye52c0f92014-04-11 01:46:06 +00001/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
Auke Kok9d5c8242008-01-24 02:22:38 -080023
24/* Linux PRO/1000 Ethernet Driver main header file */
25
26#ifndef _IGB_H_
27#define _IGB_H_
28
29#include "e1000_mac.h"
30#include "e1000_82575.h"
31
Richard Cochran74d23cc2014-12-21 19:46:56 +010032#include <linux/timecounter.h>
Patrick Ohly33af6bc2009-02-12 05:03:43 +000033#include <linux/net_tstamp.h>
Richard Cochrand339b132012-03-16 10:55:32 +000034#include <linux/ptp_clock_kernel.h>
Jiri Pirkob2cb09b2011-07-21 03:27:27 +000035#include <linux/bitops.h>
36#include <linux/if_vlan.h>
Carolyn Wyborny441fc6f2012-12-07 03:00:30 +000037#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
Carolyn Wybornycd14ef52013-12-10 07:58:34 +000039#include <linux/pci.h>
Carolyn Wybornyf4c01e92014-03-12 03:58:22 +000040#include <linux/mdio.h>
Patrick Ohly38c845c2009-02-12 05:03:41 +000041
Auke Kok9d5c8242008-01-24 02:22:38 -080042struct igb_adapter;
43
Jeff Kirsherb980ac12013-02-23 07:29:56 +000044#define E1000_PCS_CFG_IGN_SD 1
Carolyn Wyborny3860a0b2012-11-22 02:49:22 +000045
Alexander Duyck0ba82992011-08-26 07:45:47 +000046/* Interrupt defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000047#define IGB_START_ITR 648 /* ~6000 ints/sec */
48#define IGB_4K_ITR 980
49#define IGB_20K_ITR 196
50#define IGB_70K_ITR 56
Auke Kok9d5c8242008-01-24 02:22:38 -080051
Auke Kok9d5c8242008-01-24 02:22:38 -080052/* TX/RX descriptor defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000053#define IGB_DEFAULT_TXD 256
54#define IGB_DEFAULT_TX_WORK 128
55#define IGB_MIN_TXD 80
56#define IGB_MAX_TXD 4096
Auke Kok9d5c8242008-01-24 02:22:38 -080057
Jeff Kirsherb980ac12013-02-23 07:29:56 +000058#define IGB_DEFAULT_RXD 256
59#define IGB_MIN_RXD 80
60#define IGB_MAX_RXD 4096
Auke Kok9d5c8242008-01-24 02:22:38 -080061
Jeff Kirsherb980ac12013-02-23 07:29:56 +000062#define IGB_DEFAULT_ITR 3 /* dynamic */
63#define IGB_MAX_ITR_USECS 10000
64#define IGB_MIN_ITR_USECS 10
65#define NON_Q_VECTORS 1
66#define MAX_Q_VECTORS 8
Carolyn Wybornycd14ef52013-12-10 07:58:34 +000067#define MAX_MSIX_ENTRIES 10
Auke Kok9d5c8242008-01-24 02:22:38 -080068
69/* Transmit and receive queues */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000070#define IGB_MAX_RX_QUEUES 8
71#define IGB_MAX_RX_QUEUES_82575 4
72#define IGB_MAX_RX_QUEUES_I211 2
73#define IGB_MAX_TX_QUEUES 8
74#define IGB_MAX_VF_MC_ENTRIES 30
75#define IGB_MAX_VF_FUNCTIONS 8
76#define IGB_MAX_VFTA_ENTRIES 128
77#define IGB_82576_VF_DEV_ID 0x10CA
78#define IGB_I350_VF_DEV_ID 0x1520
Alexander Duyck4ae196d2009-02-19 20:40:07 -080079
Carolyn Wybornyd67974f2012-06-14 16:04:19 +000080/* NVM version defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +000081#define IGB_MAJOR_MASK 0xF000
82#define IGB_MINOR_MASK 0x0FF0
83#define IGB_BUILD_MASK 0x000F
84#define IGB_COMB_VER_MASK 0x00FF
85#define IGB_MAJOR_SHIFT 12
86#define IGB_MINOR_SHIFT 4
87#define IGB_COMB_VER_SHFT 8
88#define IGB_NVM_VER_INVALID 0xFFFF
89#define IGB_ETRACK_SHIFT 16
90#define NVM_ETRACK_WORD 0x0042
91#define NVM_COMB_VER_OFF 0x0083
92#define NVM_COMB_VER_PTR 0x003d
Carolyn Wybornyd67974f2012-06-14 16:04:19 +000093
Nathan Sullivan3f544d22016-05-03 18:10:56 -050094/* Transmit and receive latency (for PTP timestamps) */
95#define IGB_I210_TX_LATENCY_10 9542
96#define IGB_I210_TX_LATENCY_100 1024
97#define IGB_I210_TX_LATENCY_1000 178
98#define IGB_I210_RX_LATENCY_10 20662
99#define IGB_I210_RX_LATENCY_100 2213
100#define IGB_I210_RX_LATENCY_1000 448
101
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800102struct vf_data_storage {
103 unsigned char vf_mac_addresses[ETH_ALEN];
104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
105 u16 num_vf_mc_hashes;
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000106 u32 flags;
107 unsigned long last_nack;
Williams, Mitch A8151d292010-02-10 01:44:24 +0000108 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
109 u16 pf_qos;
Lior Levy17dc5662011-02-08 02:28:46 +0000110 u16 tx_rate;
Lior Levy70ea4782013-03-03 20:27:48 +0000111 bool spoofchk_enabled;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800112};
113
Yury Kylulin4827cc32017-03-07 11:20:26 +0300114/* Number of unicast MAC filters reserved for the PF in the RAR registers */
115#define IGB_PF_MAC_FILTERS_RESERVED 3
116
117struct vf_mac_filter {
118 struct list_head l;
119 int vf;
120 bool free;
121 u8 vf_mac[ETH_ALEN];
122};
123
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000124#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
Alexander Duyck7d5753f2009-10-27 23:47:16 +0000125#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
126#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
Williams, Mitch A8151d292010-02-10 01:44:24 +0000127#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
Alexander Duyckf2ca0db2009-10-27 23:46:57 +0000128
Auke Kok9d5c8242008-01-24 02:22:38 -0800129/* RX descriptor control thresholds.
130 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
131 * descriptors available in its onboard memory.
132 * Setting this to 0 disables RX descriptor prefetch.
133 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
134 * available in host memory.
135 * If PTHRESH is 0, this should also be 0.
136 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
137 * descriptors until either it has this many to write back, or the
138 * ITR timer expires.
139 */
Carolyn Wybornyceb5f132013-04-18 22:21:30 +0000140#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000141#define IGB_RX_HTHRESH 8
Carolyn Wybornyceb5f132013-04-18 22:21:30 +0000142#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000143#define IGB_TX_HTHRESH 1
144#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000145 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000146#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000147 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
Auke Kok9d5c8242008-01-24 02:22:38 -0800148
149/* this is the size past which hardware will drop packets when setting LPE=0 */
150#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
151
152/* Supported Rx Buffer Sizes */
Alexander Duyckde78d1f2012-09-25 00:31:12 +0000153#define IGB_RXBUFFER_256 256
154#define IGB_RXBUFFER_2048 2048
Alexander Duyck8649aae2017-02-06 18:27:03 -0800155#define IGB_RXBUFFER_3072 3072
Alexander Duyckde78d1f2012-09-25 00:31:12 +0000156#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
Alexander Duyckcfbc8712017-02-06 18:26:15 -0800157#define IGB_TS_HDR_LEN 16
Auke Kok9d5c8242008-01-24 02:22:38 -0800158
Alexander Duyckcfbc8712017-02-06 18:26:15 -0800159#define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
160#if (PAGE_SIZE < 8192)
161#define IGB_MAX_FRAME_BUILD_SKB \
162 (SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN)
163#else
164#define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN)
165#endif
166
Auke Kok9d5c8242008-01-24 02:22:38 -0800167/* How many Rx Buffers do we bundle into one write to the hardware ? */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000168#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
Auke Kok9d5c8242008-01-24 02:22:38 -0800169
Alexander Duyck7bd17592017-02-06 18:25:26 -0800170#define IGB_RX_DMA_ATTR \
171 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
172
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000173#define AUTO_ALL_MODES 0
174#define IGB_EEPROM_APME 0x0400
Auke Kok9d5c8242008-01-24 02:22:38 -0800175
176#ifndef IGB_MASTER_SLAVE
177/* Switch to override PHY master/slave setting */
178#define IGB_MASTER_SLAVE e1000_ms_hw_default
179#endif
180
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000181#define IGB_MNG_VLAN_NONE -1
Auke Kok9d5c8242008-01-24 02:22:38 -0800182
Alexander Duyck1d9daf42012-11-13 04:03:23 +0000183enum igb_tx_flags {
184 /* cmd_type flags */
185 IGB_TX_FLAGS_VLAN = 0x01,
186 IGB_TX_FLAGS_TSO = 0x02,
187 IGB_TX_FLAGS_TSTAMP = 0x04,
188
189 /* olinfo flags */
190 IGB_TX_FLAGS_IPV4 = 0x10,
191 IGB_TX_FLAGS_CSUM = 0x20,
192};
193
194/* VLAN info */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000195#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
Alexander Duyck2bbfebe2011-08-26 07:44:59 +0000196#define IGB_TX_FLAGS_VLAN_SHIFT 16
197
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000198/* The largest size we can write to the descriptor is 65535. In order to
Alexander Duyck21ba6fe2013-02-09 04:27:48 +0000199 * maintain a power of two alignment we have to limit ourselves to 32K.
200 */
201#define IGB_MAX_TXD_PWR 15
Jacob Kellera51d8c22016-04-13 16:08:28 -0700202#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
Alexander Duyck21ba6fe2013-02-09 04:27:48 +0000203
204/* Tx Descriptors needed, worst case */
205#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
206#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
207
Akeem G. Abodunrinf69aa392013-04-11 06:36:35 +0000208/* EEPROM byte offsets */
209#define IGB_SFF_8472_SWAP 0x5C
210#define IGB_SFF_8472_COMP 0x5E
211
212/* Bitmasks */
213#define IGB_SFF_ADDRESSING_MODE 0x4
214#define IGB_SFF_8472_UNSUP 0x00
215
Auke Kok9d5c8242008-01-24 02:22:38 -0800216/* wrapper around a pointer to a socket buffer,
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000217 * so a DMA handle can be stored along with the buffer
218 */
Alexander Duyck06034642011-08-26 07:44:22 +0000219struct igb_tx_buffer {
Alexander Duyck8542db02011-08-26 07:44:43 +0000220 union e1000_adv_tx_desc *next_to_watch;
Alexander Duyck06034642011-08-26 07:44:22 +0000221 unsigned long time_stamp;
Alexander Duyck06034642011-08-26 07:44:22 +0000222 struct sk_buff *skb;
223 unsigned int bytecount;
224 u16 gso_segs;
Alexander Duyck7af40ad92011-08-26 07:45:15 +0000225 __be16 protocol;
Carolyn Wyborny9005df32014-04-11 01:45:34 +0000226
Alexander Duyckc9f14bf32012-09-18 01:56:27 +0000227 DEFINE_DMA_UNMAP_ADDR(dma);
228 DEFINE_DMA_UNMAP_LEN(len);
Alexander Duyckebe42d12011-08-26 07:45:09 +0000229 u32 tx_flags;
Alexander Duyck06034642011-08-26 07:44:22 +0000230};
231
232struct igb_rx_buffer {
Auke Kok9d5c8242008-01-24 02:22:38 -0800233 dma_addr_t dma;
Alexander Duyck06034642011-08-26 07:44:22 +0000234 struct page *page;
Alexander Duyckbd4171a2016-12-14 15:05:34 -0800235#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
236 __u32 page_offset;
237#else
238 __u16 page_offset;
239#endif
240 __u16 pagecnt_bias;
Auke Kok9d5c8242008-01-24 02:22:38 -0800241};
242
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000243struct igb_tx_queue_stats {
Auke Kok9d5c8242008-01-24 02:22:38 -0800244 u64 packets;
245 u64 bytes;
Alexander Duyck04a5fcaa2009-10-27 15:52:27 +0000246 u64 restart_queue;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000247 u64 restart_queue2;
Auke Kok9d5c8242008-01-24 02:22:38 -0800248};
249
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000250struct igb_rx_queue_stats {
251 u64 packets;
252 u64 bytes;
253 u64 drops;
Alexander Duyck04a5fcaa2009-10-27 15:52:27 +0000254 u64 csum_err;
255 u64 alloc_failed;
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000256};
257
Alexander Duyck0ba82992011-08-26 07:45:47 +0000258struct igb_ring_container {
259 struct igb_ring *ring; /* pointer to linked list of rings */
260 unsigned int total_bytes; /* total bytes processed this int */
261 unsigned int total_packets; /* total packets processed this int */
262 u16 work_limit; /* total work allowed per interrupt */
263 u8 count; /* total number of rings in vector */
264 u8 itr; /* current ITR setting for ring */
265};
266
Alexander Duyck047e0032009-10-27 15:49:27 +0000267struct igb_ring {
Alexander Duyck238ac812011-08-26 07:43:48 +0000268 struct igb_q_vector *q_vector; /* backlink to q_vector */
269 struct net_device *netdev; /* back pointer to net_device */
270 struct device *dev; /* device pointer for dma mapping */
Alexander Duyck06034642011-08-26 07:44:22 +0000271 union { /* array of buffer info structs */
272 struct igb_tx_buffer *tx_buffer_info;
273 struct igb_rx_buffer *rx_buffer_info;
274 };
Alexander Duyck238ac812011-08-26 07:43:48 +0000275 void *desc; /* descriptor ring memory */
276 unsigned long flags; /* ring specific flags */
277 void __iomem *tail; /* pointer to ring tail register */
Alexander Duyck5536d212012-09-25 00:31:17 +0000278 dma_addr_t dma; /* phys address of the ring */
279 unsigned int size; /* length of desc. ring in bytes */
Alexander Duyck238ac812011-08-26 07:43:48 +0000280
281 u16 count; /* number of desc. in the ring */
282 u8 queue_index; /* logical index of the ring*/
283 u8 reg_idx; /* physical index of the ring */
Alexander Duyck238ac812011-08-26 07:43:48 +0000284
285 /* everything past this point are written often */
Alexander Duyck5536d212012-09-25 00:31:17 +0000286 u16 next_to_clean;
Auke Kok9d5c8242008-01-24 02:22:38 -0800287 u16 next_to_use;
Alexander Duyckcbc8e552012-09-25 00:31:02 +0000288 u16 next_to_alloc;
Auke Kok9d5c8242008-01-24 02:22:38 -0800289
Auke Kok9d5c8242008-01-24 02:22:38 -0800290 union {
291 /* TX */
292 struct {
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000293 struct igb_tx_queue_stats tx_stats;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000294 struct u64_stats_sync tx_syncp;
295 struct u64_stats_sync tx_syncp2;
Auke Kok9d5c8242008-01-24 02:22:38 -0800296 };
297 /* RX */
298 struct {
Alexander Duyck1a1c2252012-09-25 00:30:52 +0000299 struct sk_buff *skb;
Jesper Dangaard Brouer8c0ab702009-05-26 13:50:31 +0000300 struct igb_rx_queue_stats rx_stats;
Eric Dumazet12dcd862010-10-15 17:27:10 +0000301 struct u64_stats_sync rx_syncp;
Auke Kok9d5c8242008-01-24 02:22:38 -0800302 };
303 };
Alexander Duyck5536d212012-09-25 00:31:17 +0000304} ____cacheline_internodealigned_in_smp;
305
306struct igb_q_vector {
307 struct igb_adapter *adapter; /* backlink */
308 int cpu; /* CPU for DCA */
309 u32 eims_value; /* EIMS mask value */
310
311 u16 itr_val;
312 u8 set_itr;
313 void __iomem *itr_register;
314
315 struct igb_ring_container rx, tx;
316
317 struct napi_struct napi;
318 struct rcu_head rcu; /* to avoid race with update stats on free */
319 char name[IFNAMSIZ + 9];
320
321 /* for dynamic allocation of rings associated with this q_vector */
322 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
Auke Kok9d5c8242008-01-24 02:22:38 -0800323};
324
Alexander Duyck866cff02011-08-26 07:45:36 +0000325enum e1000_ring_flags_t {
Alexander Duyck8649aae2017-02-06 18:27:03 -0800326 IGB_RING_FLAG_RX_3K_BUFFER,
Alexander Duycke3cdf682017-02-06 18:27:14 -0800327 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
Alexander Duyck866cff02011-08-26 07:45:36 +0000328 IGB_RING_FLAG_RX_SCTP_CSUM,
Alexander Duyck8be10e92011-08-26 07:47:11 +0000329 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
Alexander Duyck866cff02011-08-26 07:45:36 +0000330 IGB_RING_FLAG_TX_CTX_IDX,
331 IGB_RING_FLAG_TX_DETECT_HANG
332};
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000333
Alexander Duyck8649aae2017-02-06 18:27:03 -0800334#define ring_uses_large_buffer(ring) \
335 test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
336#define set_ring_uses_large_buffer(ring) \
337 set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
338#define clear_ring_uses_large_buffer(ring) \
339 clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
340
Alexander Duycke3cdf682017-02-06 18:27:14 -0800341#define ring_uses_build_skb(ring) \
342 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
343#define set_ring_build_skb_enabled(ring) \
344 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
345#define clear_ring_build_skb_enabled(ring) \
346 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
347
Alexander Duyck8649aae2017-02-06 18:27:03 -0800348static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
349{
350#if (PAGE_SIZE < 8192)
351 if (ring_uses_large_buffer(ring))
352 return IGB_RXBUFFER_3072;
Alexander Duycke3cdf682017-02-06 18:27:14 -0800353
354 if (ring_uses_build_skb(ring))
355 return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN;
Alexander Duyck8649aae2017-02-06 18:27:03 -0800356#endif
357 return IGB_RXBUFFER_2048;
358}
359
360static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
361{
362#if (PAGE_SIZE < 8192)
363 if (ring_uses_large_buffer(ring))
364 return 1;
365#endif
366 return 0;
367}
368
369#define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
370
Alexander Duycke032afc2011-08-26 07:44:48 +0000371#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
Alexander Duyck85ad76b2009-10-27 15:52:46 +0000372
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000373#define IGB_RX_DESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000374 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000375#define IGB_TX_DESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000376 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000377#define IGB_TX_CTXTDESC(R, i) \
Alexander Duyck60136902011-08-26 07:44:05 +0000378 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
Auke Kok9d5c8242008-01-24 02:22:38 -0800379
Alexander Duyck3ceb90f2011-08-26 07:46:03 +0000380/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
381static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
382 const u32 stat_err_bits)
383{
384 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
385}
386
Alexander Duyckd7ee5b32009-10-27 15:54:23 +0000387/* igb_desc_unused - calculate if we have unused descriptors */
388static inline int igb_desc_unused(struct igb_ring *ring)
389{
390 if (ring->next_to_clean > ring->next_to_use)
391 return ring->next_to_clean - ring->next_to_use - 1;
392
393 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
394}
395
Carolyn Wybornye4288932012-12-07 03:01:42 +0000396#ifdef CONFIG_IGB_HWMON
397
398#define IGB_HWMON_TYPE_LOC 0
399#define IGB_HWMON_TYPE_TEMP 1
400#define IGB_HWMON_TYPE_CAUTION 2
401#define IGB_HWMON_TYPE_MAX 3
402
403struct hwmon_attr {
404 struct device_attribute dev_attr;
405 struct e1000_hw *hw;
406 struct e1000_thermal_diode_data *sensor;
407 char name[12];
408 };
409
410struct hwmon_buff {
Guenter Roecke3670b82013-11-26 07:15:23 +0000411 struct attribute_group group;
412 const struct attribute_group *groups[2];
413 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
414 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
Carolyn Wybornye4288932012-12-07 03:01:42 +0000415 unsigned int n_hwmon;
416 };
417#endif
418
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800419/* The number of L2 ether-type filter registers, Index 3 is reserved
420 * for PTP 1588 timestamp
421 */
422#define MAX_ETYPE_FILTER (4 - 1)
423/* ETQF filter list: one static filter per filter consumer. This is
424 * to avoid filter collisions later. Add new filters here!!
425 *
426 * Current filters: Filter 3
427 */
428#define IGB_ETQF_FILTER_1588 3
429
Richard Cochran720db4f2014-11-21 20:51:26 +0000430#define IGB_N_EXTTS 2
431#define IGB_N_PEROUT 2
432#define IGB_N_SDP 4
Laura Mihaela Vasilescuc342b392013-07-31 20:19:48 +0000433#define IGB_RETA_SIZE 128
434
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800435enum igb_filter_match_flags {
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800436 IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
Gangfeng Huang7a277a92016-07-06 13:22:56 +0800437 IGB_FILTER_FLAG_VLAN_TCI = 0x2,
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800438};
439
440#define IGB_MAX_RXNFC_FILTERS 16
441
442/* RX network flow classification data structure */
443struct igb_nfc_input {
444 /* Byte layout in order, all values with MSB first:
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800445 * match_flags - 1 byte
446 * etype - 2 bytes
Gangfeng Huang7a277a92016-07-06 13:22:56 +0800447 * vlan_tci - 2 bytes
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800448 */
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800449 u8 match_flags;
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800450 __be16 etype;
Gangfeng Huang7a277a92016-07-06 13:22:56 +0800451 __be16 vlan_tci;
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800452};
453
454struct igb_nfc_filter {
455 struct hlist_node nfc_node;
456 struct igb_nfc_input filter;
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800457 u16 etype_reg_index;
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800458 u16 sw_idx;
459 u16 action;
460};
461
Yury Kylulin83c21332017-03-07 11:20:25 +0300462struct igb_mac_addr {
463 u8 addr[ETH_ALEN];
464 u8 queue;
465 u8 state; /* bitmask */
466};
467
468#define IGB_MAC_STATE_DEFAULT 0x1
469#define IGB_MAC_STATE_IN_USE 0x2
470
Auke Kok9d5c8242008-01-24 02:22:38 -0800471/* board specific private data structure */
Auke Kok9d5c8242008-01-24 02:22:38 -0800472struct igb_adapter {
Jiri Pirkob2cb09b2011-07-21 03:27:27 +0000473 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
Alexander Duyck238ac812011-08-26 07:43:48 +0000474
475 struct net_device *netdev;
476
477 unsigned long state;
478 unsigned int flags;
479
480 unsigned int num_q_vectors;
Carolyn Wybornycd14ef52013-12-10 07:58:34 +0000481 struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000482
Auke Kok9d5c8242008-01-24 02:22:38 -0800483 /* Interrupt Throttle Rate */
Alexander Duyck4fc82ad2009-10-27 23:45:42 +0000484 u32 rx_itr_setting;
485 u32 tx_itr_setting;
Auke Kok9d5c8242008-01-24 02:22:38 -0800486 u16 tx_itr;
487 u16 rx_itr;
Auke Kok9d5c8242008-01-24 02:22:38 -0800488
Alexander Duyck238ac812011-08-26 07:43:48 +0000489 /* TX */
Alexander Duyck13fde972011-10-05 13:35:24 +0000490 u16 tx_work_limit;
Alexander Duyck238ac812011-08-26 07:43:48 +0000491 u32 tx_timeout_count;
492 int num_tx_queues;
493 struct igb_ring *tx_ring[16];
494
495 /* RX */
496 int num_rx_queues;
497 struct igb_ring *rx_ring[16];
498
499 u32 max_frame_size;
500 u32 min_frame_size;
501
502 struct timer_list watchdog_timer;
503 struct timer_list phy_info_timer;
504
505 u16 mng_vlan_id;
506 u32 bd_number;
507 u32 wol;
508 u32 en_mng_pt;
509 u16 link_speed;
510 u16 link_duplex;
511
Jarod Wilson73bf8042015-09-10 15:37:50 -0400512 u8 __iomem *io_addr; /* Mainly for iounmap use */
513
Auke Kok9d5c8242008-01-24 02:22:38 -0800514 struct work_struct reset_task;
515 struct work_struct watchdog_task;
516 bool fc_autoneg;
517 u8 tx_timeout_factor;
518 struct timer_list blink_timer;
519 unsigned long led_status;
520
Auke Kok9d5c8242008-01-24 02:22:38 -0800521 /* OS defined structs */
Auke Kok9d5c8242008-01-24 02:22:38 -0800522 struct pci_dev *pdev;
Auke Kok9d5c8242008-01-24 02:22:38 -0800523
Eric Dumazet12dcd862010-10-15 17:27:10 +0000524 spinlock_t stats64_lock;
525 struct rtnl_link_stats64 stats64;
526
Auke Kok9d5c8242008-01-24 02:22:38 -0800527 /* structs defined in e1000_hw.h */
528 struct e1000_hw hw;
529 struct e1000_hw_stats stats;
530 struct e1000_phy_info phy_info;
Auke Kok9d5c8242008-01-24 02:22:38 -0800531
532 u32 test_icr;
533 struct igb_ring test_tx_ring;
534 struct igb_ring test_rx_ring;
535
536 int msg_enable;
Alexander Duyck047e0032009-10-27 15:49:27 +0000537
Alexander Duyck047e0032009-10-27 15:49:27 +0000538 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
Auke Kok9d5c8242008-01-24 02:22:38 -0800539 u32 eims_enable_mask;
PJ Waskiewicz844290e2008-06-27 11:00:39 -0700540 u32 eims_other;
Auke Kok9d5c8242008-01-24 02:22:38 -0800541
542 /* to not mess up cache alignment, always add to the bottom */
Alexander Duyck2e5655e2009-10-27 23:50:38 +0000543 u16 tx_ring_count;
544 u16 rx_ring_count;
Alexander Duyck1bfaf072009-02-19 20:39:23 -0800545 unsigned int vfs_allocated_count;
Alexander Duyck4ae196d2009-02-19 20:40:07 -0800546 struct vf_data_storage *vf_data;
Lior Levy17dc5662011-02-08 02:28:46 +0000547 int vf_rate_link_speed;
Alexander Duycka99955f2009-11-12 18:37:19 +0000548 u32 rss_queues;
Greg Rose13800462010-11-06 02:08:26 +0000549 u32 wvbr;
Carolyn Wyborny1128c752011-10-14 00:13:49 +0000550 u32 *shadow_vfta;
Richard Cochrand339b132012-03-16 10:55:32 +0000551
552 struct ptp_clock *ptp_clock;
Matthew Vicka79f4f82012-08-10 05:40:44 +0000553 struct ptp_clock_info ptp_caps;
554 struct delayed_work ptp_overflow_work;
Matthew Vick1f6e8172012-08-18 07:26:33 +0000555 struct work_struct ptp_tx_work;
556 struct sk_buff *ptp_tx_skb;
Jacob Keller6ab5f7b2014-01-11 07:20:06 +0000557 struct hwtstamp_config tstamp_config;
Matthew Vick428f1f72012-12-13 07:20:34 +0000558 unsigned long ptp_tx_start;
Matthew Vickfc580752012-12-13 07:20:35 +0000559 unsigned long last_rx_ptp_check;
Jakub Kicinski5499a962014-04-02 10:33:33 +0000560 unsigned long last_rx_timestamp;
Jacob Keller462f1182016-05-24 13:56:27 -0700561 unsigned int ptp_flags;
Richard Cochrand339b132012-03-16 10:55:32 +0000562 spinlock_t tmreg_lock;
563 struct cyclecounter cc;
564 struct timecounter tc;
Matthew Vick428f1f72012-12-13 07:20:34 +0000565 u32 tx_hwtstamp_timeouts;
Matthew Vickfc580752012-12-13 07:20:35 +0000566 u32 rx_hwtstamp_cleared;
Jacob Kellerac28b412016-09-09 09:10:51 -0700567 bool pps_sys_wrap_on;
Matthew Vick3c89f6d2012-08-10 05:40:43 +0000568
Richard Cochran720db4f2014-11-21 20:51:26 +0000569 struct ptp_pin_desc sdp_config[IGB_N_SDP];
570 struct {
Arnd Bergmann40c9b072015-09-30 13:26:33 +0200571 struct timespec64 start;
572 struct timespec64 period;
Richard Cochran720db4f2014-11-21 20:51:26 +0000573 } perout[IGB_N_PEROUT];
574
Carolyn Wybornyd67974f2012-06-14 16:04:19 +0000575 char fw_version[32];
Carolyn Wybornye4288932012-12-07 03:01:42 +0000576#ifdef CONFIG_IGB_HWMON
Guenter Roecke3670b82013-11-26 07:15:23 +0000577 struct hwmon_buff *igb_hwmon_buff;
Carolyn Wybornye4288932012-12-07 03:01:42 +0000578 bool ets;
579#endif
Carolyn Wyborny441fc6f2012-12-07 03:00:30 +0000580 struct i2c_algo_bit_data i2c_algo;
581 struct i2c_adapter i2c_adap;
Carolyn Wyborny603e86f2013-02-20 07:40:55 +0000582 struct i2c_client *i2c_client;
Laura Mihaela Vasilescued12cc92013-07-31 20:19:54 +0000583 u32 rss_indir_tbl_init;
584 u8 rss_indir_tbl[IGB_RETA_SIZE];
Akeem G Abodunrinaa9b8cc2013-08-28 02:22:43 +0000585
586 unsigned long link_check_timeout;
Carolyn Wyborny56cec242013-10-17 05:36:26 +0000587 int copper_tries;
588 struct e1000_info ei;
Carolyn Wybornyf4c01e92014-03-12 03:58:22 +0000589 u16 eee_advert;
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800590
591 /* RX network flow classification support */
592 struct hlist_head nfc_filter_list;
593 unsigned int nfc_filter_count;
594 /* lock for RX network flow classification filter */
595 spinlock_t nfc_lock;
Gangfeng Huang64c75d42016-07-06 13:22:55 +0800596 bool etype_bitmap[MAX_ETYPE_FILTER];
Yury Kylulin83c21332017-03-07 11:20:25 +0300597
598 struct igb_mac_addr *mac_table;
Yury Kylulin4827cc32017-03-07 11:20:26 +0300599 struct vf_mac_filter vf_macs;
600 struct vf_mac_filter *vf_mac_list;
Auke Kok9d5c8242008-01-24 02:22:38 -0800601};
602
Jacob Keller462f1182016-05-24 13:56:27 -0700603/* flags controlling PTP/1588 function */
604#define IGB_PTP_ENABLED BIT(0)
Jacob Keller63737162016-05-24 13:56:28 -0700605#define IGB_PTP_OVERFLOW_CHECK BIT(1)
Jacob Keller462f1182016-05-24 13:56:27 -0700606
Jacob Kellera51d8c22016-04-13 16:08:28 -0700607#define IGB_FLAG_HAS_MSI BIT(0)
608#define IGB_FLAG_DCA_ENABLED BIT(1)
609#define IGB_FLAG_QUAD_PORT_A BIT(2)
610#define IGB_FLAG_QUEUE_PAIRS BIT(3)
611#define IGB_FLAG_DMAC BIT(4)
Jacob Kellera51d8c22016-04-13 16:08:28 -0700612#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
613#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
614#define IGB_FLAG_WOL_SUPPORTED BIT(8)
615#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
616#define IGB_FLAG_MEDIA_RESET BIT(10)
617#define IGB_FLAG_MAS_CAPABLE BIT(11)
618#define IGB_FLAG_MAS_ENABLE BIT(12)
619#define IGB_FLAG_HAS_MSIX BIT(13)
620#define IGB_FLAG_EEE BIT(14)
Alexander Duyck16903ca2016-01-06 23:11:18 -0800621#define IGB_FLAG_VLAN_PROMISC BIT(15)
Alexander Duycke0891292017-02-06 18:26:52 -0800622#define IGB_FLAG_RX_LEGACY BIT(16)
Carolyn Wyborny56cec242013-10-17 05:36:26 +0000623
624/* Media Auto Sense */
625#define IGB_MAS_ENABLE_0 0X0001
626#define IGB_MAS_ENABLE_1 0X0002
627#define IGB_MAS_ENABLE_2 0X0004
628#define IGB_MAS_ENABLE_3 0X0008
Carolyn Wyborny831ec0b2011-03-11 20:43:54 -0800629
630/* DMA Coalescing defines */
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000631#define IGB_MIN_TXPBSIZE 20408
632#define IGB_TX_BUF_4096 4096
633#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
Alexander Duyck7dfc16f2008-07-08 15:10:46 -0700634
Jeff Kirsherb980ac12013-02-23 07:29:56 +0000635#define IGB_82576_TSYNC_SHIFT 19
Auke Kok9d5c8242008-01-24 02:22:38 -0800636enum e1000_state_t {
637 __IGB_TESTING,
638 __IGB_RESETTING,
Jakub Kicinskied4420a2014-03-15 14:55:32 +0000639 __IGB_DOWN,
640 __IGB_PTP_TX_IN_PROGRESS,
Auke Kok9d5c8242008-01-24 02:22:38 -0800641};
642
643enum igb_boards {
644 board_82575,
645};
646
647extern char igb_driver_name[];
648extern char igb_driver_version[];
649
Stefan Assmann46eafa52016-02-03 09:20:50 +0100650int igb_open(struct net_device *netdev);
651int igb_close(struct net_device *netdev);
Joe Perches5ccc9212013-09-23 11:37:59 -0700652int igb_up(struct igb_adapter *);
653void igb_down(struct igb_adapter *);
654void igb_reinit_locked(struct igb_adapter *);
655void igb_reset(struct igb_adapter *);
Laura Mihaela Vasilescu907b7832013-10-01 04:33:56 -0700656int igb_reinit_queues(struct igb_adapter *);
Joe Perches5ccc9212013-09-23 11:37:59 -0700657void igb_write_rss_indir_tbl(struct igb_adapter *);
658int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
659int igb_setup_tx_resources(struct igb_ring *);
660int igb_setup_rx_resources(struct igb_ring *);
661void igb_free_tx_resources(struct igb_ring *);
662void igb_free_rx_resources(struct igb_ring *);
663void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
664void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
665void igb_setup_tctl(struct igb_adapter *);
666void igb_setup_rctl(struct igb_adapter *);
667netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
Joe Perches5ccc9212013-09-23 11:37:59 -0700668void igb_alloc_rx_buffers(struct igb_ring *, u16);
669void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
670bool igb_has_link(struct igb_adapter *adapter);
671void igb_set_ethtool_ops(struct net_device *);
672void igb_power_up_link(struct igb_adapter *);
673void igb_set_fw_version(struct igb_adapter *);
674void igb_ptp_init(struct igb_adapter *adapter);
675void igb_ptp_stop(struct igb_adapter *adapter);
676void igb_ptp_reset(struct igb_adapter *adapter);
Jacob Kellere3f23502016-05-24 13:56:30 -0700677void igb_ptp_suspend(struct igb_adapter *adapter);
Joe Perches5ccc9212013-09-23 11:37:59 -0700678void igb_ptp_rx_hang(struct igb_adapter *adapter);
Joe Perches5ccc9212013-09-23 11:37:59 -0700679void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
Alexander Duyck3456fd52017-02-06 18:26:40 -0800680void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
Joe Perches5ccc9212013-09-23 11:37:59 -0700681 struct sk_buff *skb);
Jacob Keller6ab5f7b2014-01-11 07:20:06 +0000682int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
683int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
Shota Suzuki72ddef02015-07-01 09:25:52 +0900684void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
Carolyn Wybornye4288932012-12-07 03:01:42 +0000685#ifdef CONFIG_IGB_HWMON
Joe Perches5ccc9212013-09-23 11:37:59 -0700686void igb_sysfs_exit(struct igb_adapter *adapter);
687int igb_sysfs_init(struct igb_adapter *adapter);
Carolyn Wybornye4288932012-12-07 03:01:42 +0000688#endif
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800689static inline s32 igb_reset_phy(struct e1000_hw *hw)
690{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000691 if (hw->phy.ops.reset)
692 return hw->phy.ops.reset(hw);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800693
694 return 0;
695}
696
697static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
698{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000699 if (hw->phy.ops.read_reg)
700 return hw->phy.ops.read_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800701
702 return 0;
703}
704
705static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
706{
Alexander Duycka8d2a0c2009-02-06 23:17:26 +0000707 if (hw->phy.ops.write_reg)
708 return hw->phy.ops.write_reg(hw, offset, data);
Alexander Duyckf5f4cf02008-11-21 21:30:24 -0800709
710 return 0;
711}
712
713static inline s32 igb_get_phy_info(struct e1000_hw *hw)
714{
715 if (hw->phy.ops.get_phy_info)
716 return hw->phy.ops.get_phy_info(hw);
717
718 return 0;
719}
720
Eric Dumazetbdbc0632012-01-04 20:23:36 +0000721static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
722{
723 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
724}
725
Gangfeng Huang0e71def2016-07-06 13:22:54 +0800726int igb_add_filter(struct igb_adapter *adapter,
727 struct igb_nfc_filter *input);
728int igb_erase_filter(struct igb_adapter *adapter,
729 struct igb_nfc_filter *input);
730
Auke Kok9d5c8242008-01-24 02:22:38 -0800731#endif /* _IGB_H_ */