Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * MIPS idle loop and WAIT instruction support. |
| 3 | * |
| 4 | * Copyright (C) xxxx the Anonymous |
| 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
| 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
| 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
| 14 | #include <linux/export.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <linux/irqflags.h> |
| 17 | #include <linux/printk.h> |
| 18 | #include <linux/sched.h> |
| 19 | #include <asm/cpu.h> |
| 20 | #include <asm/cpu-info.h> |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 21 | #include <asm/cpu-type.h> |
Ralf Baechle | bdc92d74 | 2013-05-21 16:59:19 +0200 | [diff] [blame] | 22 | #include <asm/idle.h> |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 23 | #include <asm/mipsregs.h> |
| 24 | |
| 25 | /* |
| 26 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, |
| 27 | * the implementation of the "wait" feature differs between CPU families. This |
| 28 | * points to the function that implements CPU specific wait. |
| 29 | * The wait instruction stops the pipeline and reduces the power consumption of |
| 30 | * the CPU very much. |
| 31 | */ |
| 32 | void (*cpu_wait)(void); |
| 33 | EXPORT_SYMBOL(cpu_wait); |
| 34 | |
| 35 | static void r3081_wait(void) |
| 36 | { |
| 37 | unsigned long cfg = read_c0_conf(); |
| 38 | write_c0_conf(cfg | R30XX_CONF_HALT); |
Ralf Baechle | fb40bc3 | 2013-05-21 14:05:27 +0200 | [diff] [blame] | 39 | local_irq_enable(); |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 40 | } |
| 41 | |
| 42 | static void r39xx_wait(void) |
| 43 | { |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 44 | if (!need_resched()) |
| 45 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); |
| 46 | local_irq_enable(); |
| 47 | } |
| 48 | |
Ralf Baechle | 087d990 | 2013-05-21 17:33:32 +0200 | [diff] [blame] | 49 | void r4k_wait(void) |
| 50 | { |
| 51 | local_irq_enable(); |
| 52 | __r4k_wait(); |
| 53 | } |
| 54 | |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 55 | /* |
| 56 | * This variant is preferable as it allows testing need_resched and going to |
| 57 | * sleep depending on the outcome atomically. Unfortunately the "It is |
| 58 | * implementation-dependent whether the pipeline restarts when a non-enabled |
| 59 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes |
| 60 | * using this version a gamble. |
| 61 | */ |
| 62 | void r4k_wait_irqoff(void) |
| 63 | { |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 64 | if (!need_resched()) |
Ralf Baechle | f91a148 | 2013-05-21 12:58:08 +0200 | [diff] [blame] | 65 | __asm__( |
| 66 | " .set push \n" |
Ralf Baechle | a809d46 | 2014-03-30 13:20:10 +0200 | [diff] [blame] | 67 | " .set arch=r4000 \n" |
Ralf Baechle | f91a148 | 2013-05-21 12:58:08 +0200 | [diff] [blame] | 68 | " wait \n" |
| 69 | " .set pop \n"); |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 70 | local_irq_enable(); |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | /* |
| 74 | * The RM7000 variant has to handle erratum 38. The workaround is to not |
| 75 | * have any pending stores when the WAIT instruction is executed. |
| 76 | */ |
| 77 | static void rm7k_wait_irqoff(void) |
| 78 | { |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 79 | if (!need_resched()) |
| 80 | __asm__( |
| 81 | " .set push \n" |
Ralf Baechle | a809d46 | 2014-03-30 13:20:10 +0200 | [diff] [blame] | 82 | " .set arch=r4000 \n" |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 83 | " .set noat \n" |
| 84 | " mfc0 $1, $12 \n" |
| 85 | " sync \n" |
| 86 | " mtc0 $1, $12 # stalls until W stage \n" |
| 87 | " wait \n" |
| 88 | " mtc0 $1, $12 # stalls until W stage \n" |
| 89 | " .set pop \n"); |
| 90 | local_irq_enable(); |
| 91 | } |
| 92 | |
| 93 | /* |
Manuel Lauss | e63a24d | 2013-06-08 19:15:41 +0000 | [diff] [blame] | 94 | * Au1 'wait' is only useful when the 32kHz counter is used as timer, |
| 95 | * since coreclock (and the cp0 counter) stops upon executing it. Only an |
| 96 | * interrupt can wake it, so they must be enabled before entering idle modes. |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 97 | */ |
| 98 | static void au1k_wait(void) |
| 99 | { |
Manuel Lauss | e63a24d | 2013-06-08 19:15:41 +0000 | [diff] [blame] | 100 | unsigned long c0status = read_c0_status() | 1; /* irqs on */ |
| 101 | |
Ralf Baechle | f91a148 | 2013-05-21 12:58:08 +0200 | [diff] [blame] | 102 | __asm__( |
Ralf Baechle | a809d46 | 2014-03-30 13:20:10 +0200 | [diff] [blame] | 103 | " .set arch=r4000 \n" |
Ralf Baechle | f91a148 | 2013-05-21 12:58:08 +0200 | [diff] [blame] | 104 | " cache 0x14, 0(%0) \n" |
| 105 | " cache 0x14, 32(%0) \n" |
| 106 | " sync \n" |
Manuel Lauss | e63a24d | 2013-06-08 19:15:41 +0000 | [diff] [blame] | 107 | " mtc0 %1, $12 \n" /* wr c0status */ |
Ralf Baechle | f91a148 | 2013-05-21 12:58:08 +0200 | [diff] [blame] | 108 | " wait \n" |
| 109 | " nop \n" |
| 110 | " nop \n" |
| 111 | " nop \n" |
| 112 | " nop \n" |
| 113 | " .set mips0 \n" |
Manuel Lauss | e63a24d | 2013-06-08 19:15:41 +0000 | [diff] [blame] | 114 | : : "r" (au1k_wait), "r" (c0status)); |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | static int __initdata nowait; |
| 118 | |
| 119 | static int __init wait_disable(char *s) |
| 120 | { |
| 121 | nowait = 1; |
| 122 | |
| 123 | return 1; |
| 124 | } |
| 125 | |
| 126 | __setup("nowait", wait_disable); |
| 127 | |
| 128 | void __init check_wait(void) |
| 129 | { |
| 130 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 131 | |
| 132 | if (nowait) { |
| 133 | printk("Wait instruction disabled.\n"); |
| 134 | return; |
| 135 | } |
| 136 | |
Paul Burton | 5b10a0e | 2015-09-22 11:24:20 -0700 | [diff] [blame] | 137 | /* |
| 138 | * MIPSr6 specifies that masked interrupts should unblock an executing |
| 139 | * wait instruction, and thus that it is safe for us to use |
| 140 | * r4k_wait_irqoff. Yippee! |
| 141 | */ |
| 142 | if (cpu_has_mips_r6) { |
| 143 | cpu_wait = r4k_wait_irqoff; |
| 144 | return; |
| 145 | } |
| 146 | |
Ralf Baechle | 69f24d1 | 2013-09-17 10:25:47 +0200 | [diff] [blame] | 147 | switch (current_cpu_type()) { |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 148 | case CPU_R3081: |
| 149 | case CPU_R3081E: |
| 150 | cpu_wait = r3081_wait; |
| 151 | break; |
| 152 | case CPU_TX3927: |
| 153 | cpu_wait = r39xx_wait; |
| 154 | break; |
| 155 | case CPU_R4200: |
| 156 | /* case CPU_R4300: */ |
| 157 | case CPU_R4600: |
| 158 | case CPU_R4640: |
| 159 | case CPU_R4650: |
| 160 | case CPU_R4700: |
| 161 | case CPU_R5000: |
| 162 | case CPU_R5500: |
| 163 | case CPU_NEVADA: |
| 164 | case CPU_4KC: |
| 165 | case CPU_4KEC: |
| 166 | case CPU_4KSC: |
| 167 | case CPU_5KC: |
Aurelien Jarno | bf463f2 | 2015-09-05 18:47:31 +0200 | [diff] [blame] | 168 | case CPU_5KE: |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 169 | case CPU_25KF: |
| 170 | case CPU_PR4450: |
| 171 | case CPU_BMIPS3300: |
| 172 | case CPU_BMIPS4350: |
| 173 | case CPU_BMIPS4380: |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 174 | case CPU_CAVIUM_OCTEON: |
| 175 | case CPU_CAVIUM_OCTEON_PLUS: |
| 176 | case CPU_CAVIUM_OCTEON2: |
David Daney | 4122af0 | 2013-07-29 15:07:02 -0700 | [diff] [blame] | 177 | case CPU_CAVIUM_OCTEON3: |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 178 | case CPU_JZRISC: |
| 179 | case CPU_LOONGSON1: |
| 180 | case CPU_XLR: |
| 181 | case CPU_XLP: |
| 182 | cpu_wait = r4k_wait; |
| 183 | break; |
Huacai Chen | b2edcfc | 2016-03-03 09:45:09 +0800 | [diff] [blame] | 184 | case CPU_LOONGSON3: |
| 185 | if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2) |
| 186 | cpu_wait = r4k_wait; |
| 187 | break; |
| 188 | |
Petri Gynther | adaa0b6 | 2015-10-19 11:44:24 -0700 | [diff] [blame] | 189 | case CPU_BMIPS5000: |
| 190 | cpu_wait = r4k_wait_irqoff; |
| 191 | break; |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 192 | case CPU_RM7000: |
| 193 | cpu_wait = rm7k_wait_irqoff; |
| 194 | break; |
| 195 | |
James Hogan | e38df28 | 2015-01-29 11:14:11 +0000 | [diff] [blame] | 196 | case CPU_PROAPTIV: |
| 197 | case CPU_P5600: |
| 198 | /* |
| 199 | * Incoming Fast Debug Channel (FDC) data during a wait |
| 200 | * instruction causes the wait never to resume, even if an |
| 201 | * interrupt is received. Avoid using wait at all if FDC data is |
| 202 | * likely to be received. |
| 203 | */ |
| 204 | if (IS_ENABLED(CONFIG_MIPS_EJTAG_FDC_TTY)) |
| 205 | break; |
| 206 | /* fall through */ |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 207 | case CPU_M14KC: |
| 208 | case CPU_M14KEC: |
| 209 | case CPU_24K: |
| 210 | case CPU_34K: |
| 211 | case CPU_1004K: |
Steven J. Hill | 442e14a | 2014-01-17 15:03:50 -0600 | [diff] [blame] | 212 | case CPU_1074K: |
Leonid Yegoshin | 26ab96d | 2013-11-27 10:07:53 +0000 | [diff] [blame] | 213 | case CPU_INTERAPTIV: |
Leonid Yegoshin | f36c472 | 2014-03-04 13:34:43 +0000 | [diff] [blame] | 214 | case CPU_M5150: |
Leonid Yegoshin | 4695089 | 2014-11-24 12:59:01 +0000 | [diff] [blame] | 215 | case CPU_QEMU_GENERIC: |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 216 | cpu_wait = r4k_wait; |
| 217 | if (read_c0_config7() & MIPS_CONF7_WII) |
| 218 | cpu_wait = r4k_wait_irqoff; |
| 219 | break; |
| 220 | |
| 221 | case CPU_74K: |
| 222 | cpu_wait = r4k_wait; |
| 223 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
| 224 | cpu_wait = r4k_wait_irqoff; |
| 225 | break; |
| 226 | |
| 227 | case CPU_TX49XX: |
| 228 | cpu_wait = r4k_wait_irqoff; |
| 229 | break; |
| 230 | case CPU_ALCHEMY: |
| 231 | cpu_wait = au1k_wait; |
| 232 | break; |
| 233 | case CPU_20KC: |
| 234 | /* |
| 235 | * WAIT on Rev1.0 has E1, E2, E3 and E16. |
| 236 | * WAIT on Rev2.0 and Rev3.0 has E16. |
| 237 | * Rev3.1 WAIT is nop, why bother |
| 238 | */ |
| 239 | if ((c->processor_id & 0xff) <= 0x64) |
| 240 | break; |
| 241 | |
| 242 | /* |
| 243 | * Another rev is incremeting c0_count at a reduced clock |
| 244 | * rate while in WAIT mode. So we basically have the choice |
| 245 | * between using the cp0 timer as clocksource or avoiding |
| 246 | * the WAIT instruction. Until more details are known, |
| 247 | * disable the use of WAIT for 20Kc entirely. |
| 248 | cpu_wait = r4k_wait; |
| 249 | */ |
| 250 | break; |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 251 | default: |
| 252 | break; |
| 253 | } |
| 254 | } |
| 255 | |
Ralf Baechle | 00baf85 | 2013-05-21 12:47:26 +0200 | [diff] [blame] | 256 | void arch_cpu_idle(void) |
| 257 | { |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 258 | if (cpu_wait) |
Ralf Baechle | c9b6869 | 2013-05-21 13:02:12 +0200 | [diff] [blame] | 259 | cpu_wait(); |
Ralf Baechle | 49f2ec9 | 2013-05-21 10:53:37 +0200 | [diff] [blame] | 260 | else |
| 261 | local_irq_enable(); |
| 262 | } |
Paul Burton | da9f970 | 2014-04-14 16:16:41 +0100 | [diff] [blame] | 263 | |
| 264 | #ifdef CONFIG_CPU_IDLE |
| 265 | |
| 266 | int mips_cpuidle_wait_enter(struct cpuidle_device *dev, |
| 267 | struct cpuidle_driver *drv, int index) |
| 268 | { |
| 269 | arch_cpu_idle(); |
| 270 | return index; |
| 271 | } |
| 272 | |
| 273 | #endif |