John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 1 | /* |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 2 | * This file contains driver for the Cadence Triple Timer Counter Rev 06 |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 3 | * |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 4 | * Copyright (C) 2011-2013 Xilinx |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 5 | * |
| 6 | * based on arch/mips/kernel/time.c timer driver |
| 7 | * |
| 8 | * This software is licensed under the terms of the GNU General Public |
| 9 | * License version 2, as published by the Free Software Foundation, and |
| 10 | * may be copied, distributed, and modified under those terms. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 18 | #include <linux/clk.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 20 | #include <linux/clockchips.h> |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 21 | #include <linux/of_address.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/slab.h> |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 24 | #include <linux/sched_clock.h> |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 25 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 26 | /* |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 27 | * This driver configures the 2 16-bit count-up timers as follows: |
| 28 | * |
| 29 | * T1: Timer 1, clocksource for generic timekeeping |
| 30 | * T2: Timer 2, clockevent source for hrtimers |
| 31 | * T3: Timer 3, <unused> |
| 32 | * |
| 33 | * The input frequency to the timer module for emulation is 2.5MHz which is |
| 34 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, |
| 35 | * the timers are clocked at 78.125KHz (12.8 us resolution). |
| 36 | |
| 37 | * The input frequency to the timer module in silicon is configurable and |
| 38 | * obtained from device tree. The pre-scaler of 32 is used. |
| 39 | */ |
| 40 | |
| 41 | /* |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 42 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 |
| 43 | * and use same offsets for Timer 2 |
| 44 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 45 | #define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */ |
| 46 | #define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */ |
| 47 | #define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */ |
| 48 | #define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */ |
| 49 | #define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */ |
| 50 | #define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */ |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 51 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 52 | #define TTC_CNT_CNTRL_DISABLE_MASK 0x1 |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 53 | |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 54 | #define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */ |
| 55 | |
Soren Brinkmann | 03377e5 | 2012-12-19 10:18:41 -0800 | [diff] [blame] | 56 | /* |
| 57 | * Setup the timers to use pre-scaling, using a fixed value for now that will |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 58 | * work across most input frequency, but it may need to be more dynamic |
| 59 | */ |
| 60 | #define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */ |
| 61 | #define PRESCALE 2048 /* The exponent must match this */ |
| 62 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) |
| 63 | #define CLK_CNTRL_PRESCALE_EN 1 |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 64 | #define CNT_CNTRL_RESET (1 << 4) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 65 | |
| 66 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 67 | * struct ttc_timer - This definition defines local timer structure |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 68 | * |
| 69 | * @base_addr: Base address of timer |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 70 | * @freq: Timer input clock frequency |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 71 | * @clk: Associated clock source |
| 72 | * @clk_rate_change_nb Notifier block for clock rate changes |
| 73 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 74 | struct ttc_timer { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 75 | void __iomem *base_addr; |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 76 | unsigned long freq; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 77 | struct clk *clk; |
| 78 | struct notifier_block clk_rate_change_nb; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 79 | }; |
| 80 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 81 | #define to_ttc_timer(x) \ |
| 82 | container_of(x, struct ttc_timer, clk_rate_change_nb) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 83 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 84 | struct ttc_timer_clocksource { |
| 85 | struct ttc_timer ttc; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 86 | struct clocksource cs; |
| 87 | }; |
| 88 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 89 | #define to_ttc_timer_clksrc(x) \ |
| 90 | container_of(x, struct ttc_timer_clocksource, cs) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 91 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 92 | struct ttc_timer_clockevent { |
| 93 | struct ttc_timer ttc; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 94 | struct clock_event_device ce; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 95 | }; |
| 96 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 97 | #define to_ttc_timer_clkevent(x) \ |
| 98 | container_of(x, struct ttc_timer_clockevent, ce) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 99 | |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 100 | static void __iomem *ttc_sched_clock_val_reg; |
| 101 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 102 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 103 | * ttc_set_interval - Set the timer interval value |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 104 | * |
| 105 | * @timer: Pointer to the timer instance |
| 106 | * @cycles: Timer interval ticks |
| 107 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 108 | static void ttc_set_interval(struct ttc_timer *timer, |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 109 | unsigned long cycles) |
| 110 | { |
| 111 | u32 ctrl_reg; |
| 112 | |
| 113 | /* Disable the counter, set the counter value and re-enable counter */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 114 | ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
| 115 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
| 116 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 117 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 118 | __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 119 | |
Soren Brinkmann | 03377e5 | 2012-12-19 10:18:41 -0800 | [diff] [blame] | 120 | /* |
| 121 | * Reset the counter (0x10) so that it starts from 0, one-shot |
| 122 | * mode makes this needed for timing to be right. |
| 123 | */ |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 124 | ctrl_reg |= CNT_CNTRL_RESET; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 125 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
| 126 | __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 130 | * ttc_clock_event_interrupt - Clock event timer interrupt handler |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 131 | * |
| 132 | * @irq: IRQ number of the Timer |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 133 | * @dev_id: void pointer to the ttc_timer instance |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 134 | * |
| 135 | * returns: Always IRQ_HANDLED - success |
| 136 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 137 | static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 138 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 139 | struct ttc_timer_clockevent *ttce = dev_id; |
| 140 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 141 | |
| 142 | /* Acknowledge the interrupt and call event handler */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 143 | __raw_readl(timer->base_addr + TTC_ISR_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 144 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 145 | ttce->ce.event_handler(&ttce->ce); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 146 | |
| 147 | return IRQ_HANDLED; |
| 148 | } |
| 149 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 150 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 151 | * __ttc_clocksource_read - Reads the timer counter register |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 152 | * |
| 153 | * returns: Current timer counter register value |
| 154 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 155 | static cycle_t __ttc_clocksource_read(struct clocksource *cs) |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 156 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 157 | struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 158 | |
| 159 | return (cycle_t)__raw_readl(timer->base_addr + |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 160 | TTC_COUNT_VAL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 161 | } |
| 162 | |
Stephen Boyd | dfded00 | 2013-11-20 00:47:32 +0100 | [diff] [blame] | 163 | static u64 notrace ttc_sched_clock_read(void) |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 164 | { |
| 165 | return __raw_readl(ttc_sched_clock_val_reg); |
| 166 | } |
| 167 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 168 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 169 | * ttc_set_next_event - Sets the time interval for next event |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 170 | * |
| 171 | * @cycles: Timer interval ticks |
| 172 | * @evt: Address of clock event instance |
| 173 | * |
| 174 | * returns: Always 0 - success |
| 175 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 176 | static int ttc_set_next_event(unsigned long cycles, |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 177 | struct clock_event_device *evt) |
| 178 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 179 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 180 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 181 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 182 | ttc_set_interval(timer, cycles); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 183 | return 0; |
| 184 | } |
| 185 | |
| 186 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 187 | * ttc_set_mode - Sets the mode of timer |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 188 | * |
| 189 | * @mode: Mode to be set |
| 190 | * @evt: Address of clock event instance |
| 191 | **/ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 192 | static void ttc_set_mode(enum clock_event_mode mode, |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 193 | struct clock_event_device *evt) |
| 194 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 195 | struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt); |
| 196 | struct ttc_timer *timer = &ttce->ttc; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 197 | u32 ctrl_reg; |
| 198 | |
| 199 | switch (mode) { |
| 200 | case CLOCK_EVT_MODE_PERIODIC: |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 201 | ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq, |
| 202 | PRESCALE * HZ)); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 203 | break; |
| 204 | case CLOCK_EVT_MODE_ONESHOT: |
| 205 | case CLOCK_EVT_MODE_UNUSED: |
| 206 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 207 | ctrl_reg = __raw_readl(timer->base_addr + |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 208 | TTC_CNT_CNTRL_OFFSET); |
| 209 | ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 210 | __raw_writel(ctrl_reg, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 211 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 212 | break; |
| 213 | case CLOCK_EVT_MODE_RESUME: |
| 214 | ctrl_reg = __raw_readl(timer->base_addr + |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 215 | TTC_CNT_CNTRL_OFFSET); |
| 216 | ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 217 | __raw_writel(ctrl_reg, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 218 | timer->base_addr + TTC_CNT_CNTRL_OFFSET); |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 219 | break; |
| 220 | } |
| 221 | } |
| 222 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 223 | static int ttc_rate_change_clocksource_cb(struct notifier_block *nb, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 224 | unsigned long event, void *data) |
| 225 | { |
| 226 | struct clk_notifier_data *ndata = data; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 227 | struct ttc_timer *ttc = to_ttc_timer(nb); |
| 228 | struct ttc_timer_clocksource *ttccs = container_of(ttc, |
| 229 | struct ttc_timer_clocksource, ttc); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 230 | |
| 231 | switch (event) { |
| 232 | case POST_RATE_CHANGE: |
| 233 | /* |
| 234 | * Do whatever is necessary to maintain a proper time base |
| 235 | * |
| 236 | * I cannot find a way to adjust the currently used clocksource |
| 237 | * to the new frequency. __clocksource_updatefreq_hz() sounds |
| 238 | * good, but does not work. Not sure what's that missing. |
| 239 | * |
| 240 | * This approach works, but triggers two clocksource switches. |
| 241 | * The first after unregister to clocksource jiffies. And |
| 242 | * another one after the register to the newly registered timer. |
| 243 | * |
| 244 | * Alternatively we could 'waste' another HW timer to ping pong |
| 245 | * between clock sources. That would also use one register and |
| 246 | * one unregister call, but only trigger one clocksource switch |
| 247 | * for the cost of another HW timer used by the OS. |
| 248 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 249 | clocksource_unregister(&ttccs->cs); |
| 250 | clocksource_register_hz(&ttccs->cs, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 251 | ndata->new_rate / PRESCALE); |
| 252 | /* fall through */ |
| 253 | case PRE_RATE_CHANGE: |
| 254 | case ABORT_RATE_CHANGE: |
| 255 | default: |
| 256 | return NOTIFY_DONE; |
| 257 | } |
| 258 | } |
| 259 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 260 | static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 261 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 262 | struct ttc_timer_clocksource *ttccs; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 263 | int err; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 264 | |
| 265 | ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); |
| 266 | if (WARN_ON(!ttccs)) |
| 267 | return; |
| 268 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 269 | ttccs->ttc.clk = clk; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 270 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 271 | err = clk_prepare_enable(ttccs->ttc.clk); |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 272 | if (WARN_ON(err)) { |
| 273 | kfree(ttccs); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 274 | return; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 275 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 276 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 277 | ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk); |
| 278 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 279 | ttccs->ttc.clk_rate_change_nb.notifier_call = |
| 280 | ttc_rate_change_clocksource_cb; |
| 281 | ttccs->ttc.clk_rate_change_nb.next = NULL; |
| 282 | if (clk_notifier_register(ttccs->ttc.clk, |
| 283 | &ttccs->ttc.clk_rate_change_nb)) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 284 | pr_warn("Unable to register clock notifier.\n"); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 285 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 286 | ttccs->ttc.base_addr = base; |
| 287 | ttccs->cs.name = "ttc_clocksource"; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 288 | ttccs->cs.rating = 200; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 289 | ttccs->cs.read = __ttc_clocksource_read; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 290 | ttccs->cs.mask = CLOCKSOURCE_MASK(16); |
| 291 | ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
| 292 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 293 | /* |
| 294 | * Setup the clock source counter to be an incrementing counter |
| 295 | * with no interrupt and it rolls over at 0xFFFF. Pre-scale |
| 296 | * it by 32 also. Let it start running now. |
| 297 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 298 | __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 299 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 300 | ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 301 | __raw_writel(CNT_CNTRL_RESET, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 302 | ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 303 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 304 | err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE); |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 305 | if (WARN_ON(err)) { |
| 306 | kfree(ttccs); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 307 | return; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 308 | } |
Soren Brinkmann | 3d77b30 | 2013-07-08 09:51:38 -0700 | [diff] [blame] | 309 | |
| 310 | ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; |
Linus Torvalds | 6c64614 | 2014-01-20 11:34:26 -0800 | [diff] [blame] | 311 | sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 312 | } |
| 313 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 314 | static int ttc_rate_change_clockevent_cb(struct notifier_block *nb, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 315 | unsigned long event, void *data) |
| 316 | { |
| 317 | struct clk_notifier_data *ndata = data; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 318 | struct ttc_timer *ttc = to_ttc_timer(nb); |
| 319 | struct ttc_timer_clockevent *ttcce = container_of(ttc, |
| 320 | struct ttc_timer_clockevent, ttc); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 321 | |
| 322 | switch (event) { |
| 323 | case POST_RATE_CHANGE: |
| 324 | { |
| 325 | unsigned long flags; |
| 326 | |
| 327 | /* |
| 328 | * clockevents_update_freq should be called with IRQ disabled on |
| 329 | * the CPU the timer provides events for. The timer we use is |
| 330 | * common to both CPUs, not sure if we need to run on both |
| 331 | * cores. |
| 332 | */ |
| 333 | local_irq_save(flags); |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 334 | clockevents_update_freq(&ttcce->ce, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 335 | ndata->new_rate / PRESCALE); |
| 336 | local_irq_restore(flags); |
| 337 | |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 338 | /* update cached frequency */ |
| 339 | ttc->freq = ndata->new_rate; |
| 340 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 341 | /* fall through */ |
| 342 | } |
| 343 | case PRE_RATE_CHANGE: |
| 344 | case ABORT_RATE_CHANGE: |
| 345 | default: |
| 346 | return NOTIFY_DONE; |
| 347 | } |
| 348 | } |
| 349 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 350 | static void __init ttc_setup_clockevent(struct clk *clk, |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 351 | void __iomem *base, u32 irq) |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 352 | { |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 353 | struct ttc_timer_clockevent *ttcce; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 354 | int err; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 355 | |
| 356 | ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL); |
| 357 | if (WARN_ON(!ttcce)) |
| 358 | return; |
| 359 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 360 | ttcce->ttc.clk = clk; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 361 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 362 | err = clk_prepare_enable(ttcce->ttc.clk); |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 363 | if (WARN_ON(err)) { |
| 364 | kfree(ttcce); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 365 | return; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 366 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 367 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 368 | ttcce->ttc.clk_rate_change_nb.notifier_call = |
| 369 | ttc_rate_change_clockevent_cb; |
| 370 | ttcce->ttc.clk_rate_change_nb.next = NULL; |
| 371 | if (clk_notifier_register(ttcce->ttc.clk, |
| 372 | &ttcce->ttc.clk_rate_change_nb)) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 373 | pr_warn("Unable to register clock notifier.\n"); |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 374 | ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 375 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 376 | ttcce->ttc.base_addr = base; |
| 377 | ttcce->ce.name = "ttc_clockevent"; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 378 | ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 379 | ttcce->ce.set_next_event = ttc_set_next_event; |
| 380 | ttcce->ce.set_mode = ttc_set_mode; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 381 | ttcce->ce.rating = 200; |
| 382 | ttcce->ce.irq = irq; |
Soren Brinkmann | 87e4ee7 | 2012-12-19 10:18:42 -0800 | [diff] [blame] | 383 | ttcce->ce.cpumask = cpu_possible_mask; |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 384 | |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 385 | /* |
| 386 | * Setup the clock event timer to be an interval timer which |
| 387 | * is prescaled by 32 using the interval interrupt. Leave it |
| 388 | * disabled for now. |
| 389 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 390 | __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 391 | __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 392 | ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); |
| 393 | __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 394 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 395 | err = request_irq(irq, ttc_clock_event_interrupt, |
Michael Opdenacker | 38c30a8 | 2013-12-09 10:12:10 +0100 | [diff] [blame] | 396 | IRQF_TIMER, ttcce->ce.name, ttcce); |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 397 | if (WARN_ON(err)) { |
| 398 | kfree(ttcce); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 399 | return; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 400 | } |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 401 | |
| 402 | clockevents_config_and_register(&ttcce->ce, |
Soren Brinkmann | c1dcc92 | 2013-11-26 17:04:50 -0800 | [diff] [blame] | 403 | ttcce->ttc.freq / PRESCALE, 1, 0xfffe); |
Josh Cartwright | 91dc985 | 2012-10-31 13:56:14 -0600 | [diff] [blame] | 404 | } |
| 405 | |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 406 | /** |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 407 | * ttc_timer_init - Initialize the timer |
John Linn | b85a3ef | 2011-06-20 11:47:27 -0600 | [diff] [blame] | 408 | * |
| 409 | * Initializes the timer hardware and register the clock source and clock event |
| 410 | * timers with Linux kernal timer framework |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 411 | */ |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 412 | static void __init ttc_timer_init(struct device_node *timer) |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 413 | { |
| 414 | unsigned int irq; |
| 415 | void __iomem *timer_baseaddr; |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 416 | struct clk *clk_cs, *clk_ce; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 417 | static int initialized; |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 418 | int clksel; |
Michal Simek | c5263bb | 2013-03-20 10:24:59 +0100 | [diff] [blame] | 419 | |
| 420 | if (initialized) |
| 421 | return; |
| 422 | |
| 423 | initialized = 1; |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 424 | |
| 425 | /* |
| 426 | * Get the 1st Triple Timer Counter (TTC) block from the device tree |
| 427 | * and use it. Note that the event timer uses the interrupt and it's the |
| 428 | * 2nd TTC hence the irq_of_parse_and_map(,1) |
| 429 | */ |
| 430 | timer_baseaddr = of_iomap(timer, 0); |
| 431 | if (!timer_baseaddr) { |
| 432 | pr_err("ERROR: invalid timer base address\n"); |
| 433 | BUG(); |
| 434 | } |
| 435 | |
| 436 | irq = irq_of_parse_and_map(timer, 1); |
| 437 | if (irq <= 0) { |
| 438 | pr_err("ERROR: invalid interrupt number\n"); |
| 439 | BUG(); |
| 440 | } |
| 441 | |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 442 | clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); |
| 443 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
| 444 | clk_cs = of_clk_get(timer, clksel); |
| 445 | if (IS_ERR(clk_cs)) { |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 446 | pr_err("ERROR: timer input clock not found\n"); |
| 447 | BUG(); |
| 448 | } |
| 449 | |
Soren Brinkmann | 30e1e28 | 2013-05-13 10:46:38 -0700 | [diff] [blame] | 450 | clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); |
| 451 | clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); |
| 452 | clk_ce = of_clk_get(timer, clksel); |
| 453 | if (IS_ERR(clk_ce)) { |
| 454 | pr_err("ERROR: timer input clock not found\n"); |
| 455 | BUG(); |
| 456 | } |
| 457 | |
| 458 | ttc_setup_clocksource(clk_cs, timer_baseaddr); |
| 459 | ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); |
Michal Simek | e932900 | 2013-03-20 10:15:28 +0100 | [diff] [blame] | 460 | |
| 461 | pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); |
| 462 | } |
| 463 | |
Michal Simek | 9e09dc5 | 2013-03-27 12:05:28 +0100 | [diff] [blame] | 464 | CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); |