| commit | 2b9c875c56f0bec92b301061fe3c2adb5e098b36 | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Thu Aug 25 14:21:56 2016 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Thu Aug 25 22:26:44 2016 +0200 |
| tree | 8dd42f812d70db69bbcfef42a99cf154e8cdd47d | |
| parent | 89af85253c32b67898c0f8bb06fe6e790e62846f [diff] |
clk: sunxi-ng: mux: Add support for mux tables Some clock muxes have holes, i.e. invalid or unconnected inputs, between parent mux values. Add support for specifying a mux table to map clock parents to mux values. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>