| commit | f83d31635cd65dd10eddaac1809b9e400d385d43 | [log] [tgz] |
|---|---|---|
| author | Dong Aisheng <aisheng.dong@nxp.com> | Wed Jun 08 22:33:36 2016 +0800 |
| committer | Shawn Guo <shawnguo@kernel.org> | Sun Jun 12 21:21:41 2016 +0800 |
| tree | 16114810176382e8255a504e5f41d58e905fbc44 | |
| parent | 147947549507fbbdbb05d4a3a24f05c2e450559f [diff] |
clk: imx: fix pll clock parents
pllx_bypass_src mux shouldn't be the parent of pllx clock
since it's only valid when when pllx BYPASS bit is set.
Thus it is actually one parent of pllx_bypass only.
Instead, pllx parent should be fixed to osc according to
reference manual.
Other plls have the same issue.
e.g. before fix, the pll tree is:
osc 6 6 24000000 0 0
pll1_bypass_src 0 0 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
After the fix, it's:
osc 6 6 24000000 0 0
pll1 0 0 792000000 0 0
pll1_bypass 0 0 792000000 0 0
pll1_sys 0 0 792000000 0 0
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>