| commit | eaaa6fb53f2652760c1c512534fe3e71672a7d78 | [log] [tgz] |
|---|---|---|
| author | Michael Turquette <mturquette@baylibre.com> | Tue Dec 22 10:12:42 2015 -0800 |
| committer | Michael Turquette <mturquette@baylibre.com> | Tue Dec 22 11:57:33 2015 -0800 |
| tree | 7d132f3caec6b261f1d86df212962eaabcf59874 | |
| parent | d90e149666258bc84e14c1c31c2064a345220cd7 [diff] | |
| parent | dfff24bde7fb8d57482e907d5dfb0be3a9e28119 [diff] |
Merge tag 'v4.5-rockchip-clk1_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Rockchip clock changes for 4.5 containing - a new pll-type used on rk3036 and other Cortex-A7 socs - new clock-trees for rk3036 and rk3228 - switch rk3288 plls to slow mode on reboot - a bunch of new clock ids - some more critical clocks - wrong register offsets for the rk3368 cpuclks - allowing more than 2 parents for the cpuclk