avr32: Generic clockevents support
This combines three patches from David Brownell:
* avr32: tclib support
* avr32: simplify clocksources
* avr32: Turn count/compare into a oneshot clockevent device
Register both TC blocks (instead of just the first one) so that
the AT32/AT91 tclib code will pick them up (instead of just the
avr32-only PIT-style clocksource).
Rename the first one and its resources appropriately.
More cleanups to the cycle counter clocksource code
- Disable all the weak symbol magic; remove the AVR32-only TCB-based
clocksource code (source and header).
- Mark the __init code properly.
- Don't forget to report IRQF_TIMER.
- Make the system work properly with this clocksource, by preventing
use of the CPU "idle" sleep state in the idle loop when it's used.
Package the avr32 count/compare timekeeping support as a oneshot
clockevent device, so it supports NO_HZ and high res timers.
This means it also supports plugging in other clockevent devices
and clocksources.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
index bf2f762..00a9862 100644
--- a/arch/avr32/kernel/time.c
+++ b/arch/avr32/kernel/time.c
@@ -1,16 +1,12 @@
/*
* Copyright (C) 2004-2007 Atmel Corporation
*
- * Based on MIPS implementation arch/mips/kernel/time.c
- * Copyright 2001 MontaVista Software Inc.
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-
#include <linux/clk.h>
-#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <linux/time.h>
#include <linux/module.h>
#include <linux/interrupt.h>
@@ -27,13 +23,10 @@
#include <asm/io.h>
#include <asm/sections.h>
-/* how many counter cycles in a jiffy? */
-static u32 cycles_per_jiffy;
+#include <asm/arch/pm.h>
-/* the count value for the next timer interrupt */
-static u32 expirelo;
-cycle_t __weak read_cycle_count(void)
+static cycle_t read_cycle_count(void)
{
return (cycle_t)sysreg_read(COUNT);
}
@@ -42,10 +35,11 @@
* The architectural cycle count registers are a fine clocksource unless
* the system idle loop use sleep states like "idle": the CPU cycles
* measured by COUNT (and COMPARE) don't happen during sleep states.
+ * Their duration also changes if cpufreq changes the CPU clock rate.
* So we rate the clocksource using COUNT as very low quality.
*/
-struct clocksource __weak clocksource_avr32 = {
- .name = "avr32",
+static struct clocksource counter = {
+ .name = "avr32_counter",
.rating = 50,
.read = read_cycle_count,
.mask = CLOCKSOURCE_MASK(32),
@@ -53,152 +47,109 @@
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
-
-struct irqaction timer_irqaction = {
- .handler = timer_interrupt,
- .flags = IRQF_DISABLED,
- .name = "timer",
-};
-
-static void avr32_timer_ack(void)
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
- u32 count;
-
- /* Ack this timer interrupt and set the next one */
- expirelo += cycles_per_jiffy;
- /* setting COMPARE to 0 stops the COUNT-COMPARE */
- if (expirelo == 0) {
- sysreg_write(COMPARE, expirelo + 1);
- } else {
- sysreg_write(COMPARE, expirelo);
- }
-
- /* Check to see if we have missed any timer interrupts */
- count = sysreg_read(COUNT);
- if ((count - expirelo) < 0x7fffffff) {
- expirelo = count + cycles_per_jiffy;
- sysreg_write(COMPARE, expirelo);
- }
-}
-
-int __weak avr32_hpt_init(void)
-{
- int ret;
- unsigned long mult, shift, count_hz;
-
- count_hz = clk_get_rate(boot_cpu_data.clk);
- shift = clocksource_avr32.shift;
- mult = clocksource_hz2mult(count_hz, shift);
- clocksource_avr32.mult = mult;
-
- {
- u64 tmp;
-
- tmp = TICK_NSEC;
- tmp <<= shift;
- tmp += mult / 2;
- do_div(tmp, mult);
-
- cycles_per_jiffy = tmp;
- }
-
- ret = setup_irq(0, &timer_irqaction);
- if (ret) {
- pr_debug("timer: could not request IRQ 0: %d\n", ret);
- return -ENODEV;
- }
-
- printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
- "%lu.%03lu MHz\n",
- ((count_hz + 500) / 1000) / 1000,
- ((count_hz + 500) / 1000) % 1000);
-
- return 0;
-}
-
-/*
- * Taken from MIPS c0_hpt_timer_init().
- *
- * The reason COUNT is written twice is probably to make sure we don't get any
- * timer interrupts while we are messing with the counter.
- */
-int __weak avr32_hpt_start(void)
-{
- u32 count = sysreg_read(COUNT);
- expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
- sysreg_write(COUNT, expirelo - cycles_per_jiffy);
- sysreg_write(COMPARE, expirelo);
- sysreg_write(COUNT, count);
-
- return 0;
-}
-
-/*
- * local_timer_interrupt() does profiling and process accounting on a
- * per-CPU basis.
- *
- * In UP mode, it is invoked from the (global) timer_interrupt.
- */
-void local_timer_interrupt(int irq, void *dev_id)
-{
- if (current->pid)
- profile_tick(CPU_PROFILING);
- update_process_times(user_mode(get_irq_regs()));
-}
-
-irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
-{
- /* ack timer interrupt and try to set next interrupt */
- avr32_timer_ack();
+ struct clock_event_device *evdev = dev_id;
/*
- * Call the generic timer interrupt handler
+ * Disable the interrupt until the clockevent subsystem
+ * reprograms it.
*/
- write_seqlock(&xtime_lock);
- do_timer(1);
- write_sequnlock(&xtime_lock);
+ sysreg_write(COMPARE, 0);
- /*
- * In UP mode, we call local_timer_interrupt() to do profiling
- * and process accounting.
- *
- * SMP is not supported yet.
- */
- local_timer_interrupt(irq, dev_id);
-
+ evdev->event_handler(evdev);
return IRQ_HANDLED;
}
+static struct irqaction timer_irqaction = {
+ .handler = timer_interrupt,
+ .flags = IRQF_TIMER | IRQF_DISABLED,
+ .name = "avr32_comparator",
+};
+
+static int comparator_next_event(unsigned long delta,
+ struct clock_event_device *evdev)
+{
+ unsigned long flags;
+
+ raw_local_irq_save(flags);
+
+ /* The time to read COUNT then update COMPARE must be less
+ * than the min_delta_ns value for this clockevent source.
+ */
+ sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
+
+ raw_local_irq_restore(flags);
+
+ return 0;
+}
+
+static void comparator_mode(enum clock_event_mode mode,
+ struct clock_event_device *evdev)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ pr_debug("%s: start\n", evdev->name);
+ /* FALLTHROUGH */
+ case CLOCK_EVT_MODE_RESUME:
+ cpu_disable_idle_sleep();
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ sysreg_write(COMPARE, 0);
+ pr_debug("%s: stop\n", evdev->name);
+ cpu_enable_idle_sleep();
+ break;
+ default:
+ BUG();
+ }
+}
+
+static struct clock_event_device comparator = {
+ .name = "avr32_comparator",
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 16,
+ .rating = 50,
+ .cpumask = CPU_MASK_CPU0,
+ .set_next_event = comparator_next_event,
+ .set_mode = comparator_mode,
+};
+
void __init time_init(void)
{
+ unsigned long counter_hz;
int ret;
- /*
- * Make sure we don't get any COMPARE interrupts before we can
- * handle them.
- */
- sysreg_write(COMPARE, 0);
-
xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
xtime.tv_nsec = 0;
set_normalized_timespec(&wall_to_monotonic,
-xtime.tv_sec, -xtime.tv_nsec);
- ret = avr32_hpt_init();
- if (ret) {
- pr_debug("timer: failed setup: %d\n", ret);
- return;
- }
+ /* figure rate for counter */
+ counter_hz = clk_get_rate(boot_cpu_data.clk);
+ counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
- ret = clocksource_register(&clocksource_avr32);
+ ret = clocksource_register(&counter);
if (ret)
pr_debug("timer: could not register clocksource: %d\n", ret);
- ret = avr32_hpt_start();
- if (ret) {
- pr_debug("timer: failed starting: %d\n", ret);
- return;
+ /* setup COMPARE clockevent */
+ comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
+ comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
+ comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
+
+ sysreg_write(COMPARE, 0);
+ timer_irqaction.dev_id = &comparator;
+
+ ret = setup_irq(0, &timer_irqaction);
+ if (ret)
+ pr_debug("timer: could not request IRQ 0: %d\n", ret);
+ else {
+ clockevents_register_device(&comparator);
+
+ pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
+ ((counter_hz + 500) / 1000) / 1000,
+ ((counter_hz + 500) / 1000) % 1000);
}
}