tree 9b1df8a76713d55ca08d11bd212281b11f6af652
parent 23e55f92d4fd733365dd572ea6e9e211387123c2
author Kumar Gala <galak@kernel.crashing.org> 1251129168 +0000
committer Benjamin Herrenschmidt <benh@kernel.crashing.org> 1251433452 +1000

powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers

Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.

We currently only used paired MAS registers to access the full RPN + perm
bits that are kept in MAS7||MAS3.  We assume that if an implementation has
hardware page table at this time it also implements in TLB reservations.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>