| commit | d887a1ce285f03c689bb4fbbaf574160bb484c3e | [log] [tgz] |
|---|---|---|
| author | Michael Hennerich <michael.hennerich@analog.com> | Fri Sep 25 09:03:21 2009 +0000 |
| committer | Mike Frysinger <vapier@gentoo.org> | Tue Dec 15 00:14:00 2009 -0500 |
| tree | cb1bfea50d25294c7a4c1c886f1b0b5aab743016 | |
| parent | 21b03cfe4c50fd586bfebd06d852457c07f60c2b [diff] |
Blackfin: cpufreq: use a constant latency PLL_LOCKCNT applies only to the PLL programming sequence which does not apply to core and system clock dividers. Writes to PLL_DIV to change the CSEL/SSEL dividers take effect immediately. There is still overhead in software in writing the new dividers, so just use a value of 50us as this should be good enough. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>