tree 7d3d95f3ea4edfc07c5189b3211b242f6f5d61a7
parent 4c0657ae432398f729c1d402bab935505a5255b5
author Guoying Zhang <Guoying.Zhang@csr.com> 1441794632 +0000
committer Wolfram Sang <wsa@the-dreams.de> 1445633325 +0200

i2c: sirf: tune the divider to make i2c bus freq more accurate

In prima2 and atlas7, due to some hardware design issue. we
need to adjust the divider ratio a little according to i2c
bus frequency ranges.
Since i2c is open drain interface that allows the slave to
stall the transaction by holding the SCL line at '0', the RTL
implementation is waiting for SCL feedback from the pin after
setting it to High-Z ('1'). This wait adds to the high-time
interval counter few cycles of the input synchronization
(depending on the SCL_FILTER_REG field), and also the time it
takes for the board pull-up resistor to rise the SCL line.
For slow SCL settings these additions are negligible, but they
start to affect the speed when clock is set to faster frequencies.
This patch is based on the actual tests, and it makes SCL more
accurate.

Signed-off-by: Guoying Zhang <Guoying.Zhang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>