tree 4b0ba3c3a5335e844edbf97403c12b88b04f69d5
parent d7a512bfe0be3790bae8465b4cb6c1bbca03c616
author Vineet Gupta <vgupta@synopsys.com> 1428321237 +0530
committer Vineet Gupta <vgupta@synopsys.com> 1434962215 +0530

ARCv2: MMUv4: cache programming model changes

Caveats about cache flush on ARCv2 based cores

- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
  need to setup PTAG reg

- icache is still VIPT but only aliasing configs need PTAG setup

So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>