tree adaef931f4064d2969ca78d987dccace85607d3a
parent 65f6ecc93e7cca888a96a68cf6b5292dff1982b6
author Hariprasad Shenai <hariprasad@chelsio.com> 1415360190 +0530
committer David S. Miller <davem@davemloft.net> 1415646903 -0500

cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers

T5 introduces the ability to have separate Packing and Padding Boundaries
for SGE DMA transfers from the chip to Host Memory. This change set takes
advantage of that to set up a smaller Padding Boundary to conserve PCI Link
and Memory Bandwidth with T5.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>