commit c6d34eddecb34fd84f9fb2ea26a63cfde5662f49
author Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Thu Apr 15 13:09:13 2010 +0900
committer Jesse Barnes <jbarnes@virtuousgeek.org> Tue May 11 12:01:12 2010 -0700
tree a80ed52485693d649158621edcd8bd2d9431d3c9
parent d4dfd7278eade24c4aa4b36b8df981fab04f2f26

PCI: aerdrv: RsvdP of PCI_ERR_ROOT_COMMAND

Handle preserved bits properly.

Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

drivers/pci/pcie/aer/aerdrv.c

diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 7a711ee..4e845ab 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -234,13 +234,15 @@
 static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
 {
 	u16 p2p_ctrl;
-	u32 status;
+	u32 reg32;
 	int pos;
 
 	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 
 	/* Disable Root's interrupt in response to error messages */
-	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 0);
+	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
+	reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
+	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
 	/* Assert Secondary Bus Reset */
 	pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &p2p_ctrl);
@@ -265,12 +267,14 @@
 	msleep(200);
 	dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
 
+	/* Clear Root Error Status */
+	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
+	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, reg32);
+
 	/* Enable Root Port's interrupt in response to error messages */
-	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);
-	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, status);
-	pci_write_config_dword(dev,
-		pos + PCI_ERR_ROOT_COMMAND,
-		ROOT_PORT_INTR_ON_MESG_MASK);
+	pci_read_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
+	reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
+	pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
 	return PCI_ERS_RESULT_RECOVERED;
 }

drivers/pci/pcie/aer/aerdrv_core.c

diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index aceb04b..9754a09 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -623,9 +623,9 @@
 	set_downstream_devices_error_reporting(pdev, true);
 
 	/* Enable Root Port's interrupt in response to error messages */
-	pci_write_config_dword(pdev,
-		aer_pos + PCI_ERR_ROOT_COMMAND,
-		ROOT_PORT_INTR_ON_MESG_MASK);
+	pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, &reg32);
+	reg32 |= ROOT_PORT_INTR_ON_MESG_MASK;
+	pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, reg32);
 }
 
 /**
@@ -648,7 +648,9 @@
 
 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 	/* Disable Root's interrupt in response to error messages */
-	pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0);
+	pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, &reg32);
+	reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
+	pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
 	/* Clear Root's error status reg */
 	pci_read_config_dword(pdev, pos + PCI_ERR_ROOT_STATUS, &reg32);