tree cd5114edfeb1f1dd4ae30f886f176236c5e5eb84
parent cc937e5e4bcf6c97746384e5c07dd2b2c45898b3
author Archit Taneja <archit@ti.com> 1340694511 +0530
committer Tomi Valkeinen <tomi.valkeinen@ti.com> 1340954154 +0300

OMAPDSS: DSI: Fix HSYNC, VSYNC and DE polarities between DISPC and DSI

For DSI operation in videomode, DISPC logic levels for the signals HSYNC, VSYNC
and DE need to be specified to DSI via the fields VP_HSYNC_POL, VP_VSYNC_POL and
VP_DE_POL in DSI_CTRL registers.

This information is completely internal to DSS as logic levels for the above
signals hold no meaning on the DSI bus. Hence a DSI panel driver should be
totally oblivious of these fields.

Fix the logic levels/polarities in the DISPC and DSI registers to a default
value. This is done by overriding these fields in omap_video_timings struct
filled by the panel driver for DISPC, and use the equivalent default values
when programming DSI_CTRL registers. Also, remove the redundant polarity related
fields in omap_dss_dsi_videomode_data.

Signed-off-by: Archit Taneja <archit@ti.com>