tree 9072b01dd90206a5908274e8d91337c1ca41badf
parent 5e79cb29ddbd1d354398308309337ba013245469
author Minghuan Lian <Minghuan.Lian@nxp.com> 1458731300 +0800
committer Marc Zyngier <marc.zyngier@arm.com> 1462352284 +0100

irqchip: Add Layerscape SCFG MSI controller support

Some kind of Freescale Layerscape SoC provides a MSI
implementation which uses two SCFG registers MSIIR and
MSIR to support 32 MSI interrupts for each PCIe controller.
The patch is to support it.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>