tree ac0b962debf44ef6a15a6ea0a652633f1afe372f
parent bd603455f366bd66a5e1870bc285c05c9cb6a72d
author Mark Langsdorf <mark.langsdorf@calxeda.com> 1359389593 +0000
committer Rafael J. Wysocki <rafael.j.wysocki@intel.com> 1359759675 +0100

clk / highbank: Prevent glitches in non-bypass reset mode

The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>