tree 9f878b4eac616d505dc03e13598f52e0fe9054c5
parent 026e2c05ef58ef413e2d52696f125d5ea1aa8bce
author Mark Langsdorf <mark.langsdorf@amd.com> 1216415032 -0500
committer Ingo Molnar <mingo@elte.hu> 1217254663 +0200

x86: L3 cache index disable for 2.6.26

New versions of AMD processors have support to disable parts
of their L3 caches if too many MCEs are generated by the
L3 cache.

This patch provides a /sysfs interface under the cache
hierarchy to display which caches indices are disabled
(if any) and to monitoring applications to disable a
cache index.

This patch does not set an automatic policy to disable
the L3 cache.  Policy decisions would need to be made
by a RAS handler.  This patch merely makes it easier to
see what indices are currently disabled.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>