| commit | 89683fdefdd74828145b9d18333761cc975143f8 | [log] [tgz] |
|---|---|---|
| author | Peter Ujfalusi <peter.ujfalusi@ti.com> | Thu Jun 04 16:04:16 2015 +0300 |
| committer | Mark Brown <broonie@kernel.org> | Thu Jun 04 17:50:02 2015 +0100 |
| tree | baccb272b4134abd5a49d2341739f743f7d14408 | |
| parent | 1cf0f44811b754b64283b11ef0e60cb0de07b29c [diff] |
ASoC: tas2552: Correct PDM configuration register bit definitions The PDM clock can be selected via bit0-1. PDM_DATA_ES bit is at bit2. The code were trying to select BCLK as PDM reference clock but instead it was selecting PLL and set the DATA_ES bit to 1. Selecting the PLL output as reference clock as default does make sense, but the driver should not change the PDM data edge. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>