| commit | 81fbf101f2858e63bbb380447a76870924b84653 | [log] [tgz] |
|---|---|---|
| author | Ruchika Kharwar <ruchika@ti.com> | Thu May 30 14:54:09 2013 -0500 |
| committer | Felipe Balbi <balbi@ti.com> | Sat Jun 01 00:22:49 2013 +0300 |
| tree | 5146e6b96361157dd674b5f0ca5109f728d8d4ae | |
| parent | f016a16d8c1f6cd0567a88d0a5843aab385e969a [diff] |
usb: phy: omap-usb3: updated dpll M,N values to support DRA7xx devices Addition of the M and N recommended values for the USB3 PHY DPLL. Sysclk for DRA7xx is 20MHz. This yields: Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz Signed-off-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Felipe Balbi <balbi@ti.com>