tree b4cb8211acf56f2f8acc7ef1429cee4e667f2834
parent a5c8b52abe677977883655166796f167ef1e0084
author Vineet Gupta <vgupta@synopsys.com> 1428053827 +0300
committer Vineet Gupta <vgupta@synopsys.com> 1435192219 +0530

ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)

L2 cache on ARCHS processors is called SLC (System Level Cache)
For working DMA (in absence of hardware assisted IO Coherency) we need
to manage SLC explicitly when buffers transition between cpu and
controllers.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>