tree 831b7793cabc8dc01ad3cad05f7abf1b0ac99e6b
parent 80605c6513207344d00b32e8d1e64bd34fdf1358
author John Fastabend <john.r.fastabend@intel.com> 1303802758 +0000
committer Jeff Kirsher <jeffrey.t.kirsher@intel.com> 1308644367 -0700

ixgbe: consolidate MRQC and MTQC handling

The MRQC and MTQC registers are configured in the main
setup path but are also reconfigured in the DCB setup
path. The DCB path fixes the DCB configuration by configuring
the SECTXMINIFG gap which is required for DCB pause
to operate correctly.

This patch reduces the duplicate code and does all setup
in ixgbe_setup_mtqc() and ixgbe_setup_mrqc().

Additionally, this removes the IXGBE_QDE. This write never
set the WRITE bit in the register so the write was not
actually doing anything. Also this was to clear the register
but, it is never set and defaults to zero. If this is
needed for SRIOV it should be added correctly in a follow
up patch. But it's never been working so removing it here
should be OK.

Signed-off-by: John Fastabend <john.r.fastabend@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>