tree a558860eda063760e331be9389c77f34dc7cde94
parent 6089ef19c9dadaf0e3378f75eca65af861cd3974
author Chen-Yu Tsai <wens@csie.org> 1422388447 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1424679954 +0100

clk: sunxi: Add support for sun9i A80 USB clocks and resets

The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.

Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>