tree 390279203a8c73a986d15be5cc30f9bb2e95c1e8
parent 6d84b986b26bac1d4d678ff10c10a633bf53f834
author Ben Hutchings <bhutchings@solarflare.com> 1298395570 +0000
committer Ben Hutchings <bhutchings@solarflare.com> 1299261522 +0000

sfc: Use write-combining to reduce TX latency

Based on work by Neil Turton <nturton@solarflare.com> and
Kieran Mansley <kmansley@solarflare.com>.

The BIU has now been verified to handle 3- and 4-dword writes within a
single 128-bit register correctly.  This means we can enable write-
combining and only insert write barriers between writes to distinct
registers.

This has been observed to save about 0.5 us when pushing a TX
descriptor to an empty TX queue.

Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>