tree af36d43870e098bfea1b3a8b1e9a22c8dd93832a
parent 44a6f3dbf1ac63b4d689cf081a3540cde03aa5d5
author Thierry Reding <treding@nvidia.com> 1427104666 +0100
committer Thierry Reding <treding@nvidia.com> 1428674658 +0200

clk: tegra: Register the proper number of resets

The number of resets controls is 32 times the number of peripheral
register banks rather than 32 times the number of clocks. This reduces
(drastically) the number of reset controls registered from 10080 (315
clocks * 32) to 224 (6 peripheral register banks * 32).

This also fixes a potential crash because trying to use any of the
excess reset controls (224-10079) would have caused accesses beyond
the array bounds of the peripheral register banks definition array.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Fixes: 6d5b988e7dc5 ("clk: tegra: implement a reset driver")
Cc: stable@vger.kernel.org # 3.14+
Signed-off-by: Thierry Reding <treding@nvidia.com>