tree a3e361dd4f1183b4977129cf571d34ea229245ce
parent 61e6cfa80de5760bbe406f4e815b7739205754d2
author Stephen Warren <swarren@nvidia.com> 1381527797 -0600
committer Mark Brown <broonie@linaro.org> 1381758987 +0100

ASoC: tegra: support new register layouts in Tegra124

Tegra124 introduces some small changes to the layout of some registers.
Modify the affected drivers to program those registers appropriately
based on which SoC they're running on.

Tegra124 also introduced some new modules on the AHUB configlink register
bus. These will require new entries in configlink_clocks[] in the AHUB
driver. However, supporting that change likely relies on switching Tegra
to the common reset framework, so I'll defer that change for now.

Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>