| commit | 2aba76f014a7b56ab4fe75845c5fd57b5590acc2 | [log] [tgz] |
|---|---|---|
| author | Michael Williamson <michael.williamson@criticallink.com> | Fri May 20 10:26:06 2011 -0400 |
| committer | Liam Girdwood <lrg@ti.com> | Sat May 21 12:07:56 2011 +0100 |
| tree | 67cd2be68adce646b25b74e6e52bb6cc4f25f6c7 | |
| parent | 4a787a3ff3f419c23ab0a5cef677fa441356b818 [diff] |
audio: tlv320aic26: fix PLL register configuration The current PLL configuration code for the tlc320aic26 codec appears to assume a hardcoded system clock of 12 MHz. Use the clock value provided by the DAI_OPS API for the calculation. Tested using a MityDSP-L138 platform providing a 24.576 MHz clock. Signed-off-by: Michael Williamson <michael.williamson@criticallink.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@ti.com>