tree da5a5e262f641d6e48db936295c79932901d7084
parent f81309067ff2d84788316c513a415f6bb8c9171f
author Russell King <rmk+kernel@arm.linux.org.uk> 1433333416 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1437834491 +0100

ARM: add soc memory barrier extension

Add an extension to the heavy barrier code to allow a SoC specific
memory barrier function to be provided.  This is needed for platforms
where the interconnect has weak ordering, and thus needs assistance
to ensure that memory writes are properly visible in the correct order
to other parts of the system.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>