tree 337f7c7f00c68c84d696ca00c3d61dde4ab6f8ae
parent 02ae2bc6febd90cf3de61b6a1bdf491966ed410f
author Chen-Yu Tsai <wens@csie.org> 1492049633 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1492075324 +0200

clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate change

This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should mitigate the system
hangs observed after the introduction of cpufreq for the A33.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>