sh: CPU flags in AT_HWCAP in ELF auxvt.
Encode processor flags in AT_HWCAP in the ELF auxiliary vector.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6e8a2b5..0e65aa6 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -76,6 +76,7 @@
cpu_data->type = CPU_SH73180;
cpu_data->icache.ways = 4;
cpu_data->dcache.ways = 4;
+ cpu_data->flags |= CPU_HAS_LLSC;
break;
case 0x2001:
case 0x2004:
@@ -83,7 +84,7 @@
cpu_data->icache.ways = 4;
cpu_data->dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_FPU;
+ cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
break;
case 0x2006:
case 0x200A:
@@ -95,13 +96,15 @@
cpu_data->icache.ways = 4;
cpu_data->dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER;
+ cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+ CPU_HAS_LLSC;
break;
case 0x3000:
case 0x3003:
cpu_data->type = CPU_SH7343;
cpu_data->icache.ways = 4;
cpu_data->dcache.ways = 4;
+ cpu_data->flags |= CPU_HAS_LLSC;
break;
case 0x8000:
cpu_data->type = CPU_ST40RA;
@@ -180,4 +183,3 @@
return 0;
}
-
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
new file mode 100644
index 0000000..e398947
--- /dev/null
+++ b/include/asm-sh/cpu-features.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_SH_CPU_FEATURES_H
+#define __ASM_SH_CPU_FEATURES_H
+
+/*
+ * Processor flags
+ */
+#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
+#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
+#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
+#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
+#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
+#define CPU_HAS_PTEA 0x0020 /* PTEA register */
+#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
+
+#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
index 1b63dfe..cc8e5e7 100644
--- a/include/asm-sh/elf.h
+++ b/include/asm-sh/elf.h
@@ -1,6 +1,11 @@
#ifndef __ASM_SH_ELF_H
#define __ASM_SH_ELF_H
+#include <asm/processor.h>
+#include <asm/auxvec.h>
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
/* SH relocation types */
#define R_SH_NONE 0
#define R_SH_DIR32 1
@@ -46,9 +51,6 @@
* ELF register definitions..
*/
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
@@ -91,7 +93,7 @@
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
-#define ELF_HWCAP (0)
+#define ELF_HWCAP (boot_cpu_data.flags)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 3b3ef4f..bdd47270 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -14,6 +14,7 @@
#include <asm/types.h>
#include <asm/cache.h>
#include <asm/ptrace.h>
+#include <asm/cpu-features.h>
/*
* Default implementation of macro that returns current
@@ -127,17 +128,6 @@
struct sh_fpu_soft_struct soft;
};
-/*
- * Processor flags
- */
-
-#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
-#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
-#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
-#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
-#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
-#define CPU_HAS_PTEA 0x0020 /* PTEA register */
-
struct thread_struct {
unsigned long sp;
unsigned long pc;