| commit | 2d02b8bdba322b527c5f5168ce1ca10c2d982a78 | [log] [tgz] |
|---|---|---|
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | Fri Feb 26 15:29:32 2016 -0600 |
| committer | Dave Airlie <airlied@redhat.com> | Wed Mar 02 17:50:17 2016 +1000 |
| tree | 562afede287656dae0c54d491c7b76a6c067080b | |
| parent | ead8f34c701ec7bf3234118b8c746227f30dfd1a [diff] |
drm/ast: Fix incorrect register check for DRAM width During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>