commit 260a1fd26c62af482a22c6b31cc7882b4ec980d2
author Holger Schurig <hs4233@mail.mn-solutions.de> Mon Jan 26 16:34:53 2009 +0100
committer Sascha Hauer <s.hauer@pengutronix.de> Fri Mar 13 10:33:53 2009 +0100
tree 358b432297a42123ac3970999ac9e1add47d5dd2
parent 058b7a6f465bebd87c1f295afdd56cc6a33dffbd

arm/imx2x: split i.MX21/i.MX27 register definitions

* define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to
  CONFIG_ARCH_MX27, but this might change)
* splits one header file. Memory definitions, interrupt sources,
  DMA channels are split into common part, i.MX27 specific and i.MX21
  specific.
* guard access to UART5/UART6, which don't exist on i.MX21

Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

arch/arm/plat-mxc/include/mach/mxc.h

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index bbd848e00..d6b0c47 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -37,6 +37,10 @@
 # define cpu_is_mx27() (0)
 #endif
 
+#ifndef CONFIG_MACH_MX21
+# define cpu_is_mx21() (0)
+#endif
+
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)