OMAPDSS: Add interlace parameter to omap_video_timings

Add a parameter called interlace which tells whether the timings are in
interlaced or progressive mode. This aligns the omap_video_timings struct with
the Xorg modeline configuration.

It also removes the hack needed to write to divide the manager height by 2 if
the connected interface is VENC.

Signed-off-by: Archit Taneja <archit@ti.com>
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 957c049..d200f44 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -2754,11 +2754,7 @@
 
 		DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
 	} else {
-		enum dss_hdmi_venc_clk_source_select source;
-
-		source = dss_get_hdmi_venc_clk_source();
-
-		if (source == DSS_VENC_TV_CLK)
+		if (t.interlace == true)
 			t.y_res /= 2;
 	}
 
diff --git a/drivers/video/omap2/dss/hdmi_panel.c b/drivers/video/omap2/dss/hdmi_panel.c
index 723a137..e10844f 100644
--- a/drivers/video/omap2/dss/hdmi_panel.c
+++ b/drivers/video/omap2/dss/hdmi_panel.c
@@ -46,6 +46,7 @@
 	dssdev->panel.timings = (struct omap_video_timings)
 			{ 640, 480, 25175, 96, 16, 48, 2, 11, 31,
 				OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
+				false,
 			};
 
 	DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n",
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 416d478..3a22087 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -272,6 +272,8 @@
 	.vsw		= 5,
 	.vfp		= 5,
 	.vbp		= 41,
+
+	.interlace	= true,
 };
 EXPORT_SYMBOL(omap_dss_pal_timings);
 
@@ -285,6 +287,8 @@
 	.vsw		= 6,
 	.vfp		= 6,
 	.vbp		= 31,
+
+	.interlace	= true,
 };
 EXPORT_SYMBOL(omap_dss_ntsc_timings);
 
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 14f261b..d8ab944 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -344,6 +344,8 @@
 	enum omap_dss_signal_level vsync_level;
 	/* Hsync logic level */
 	enum omap_dss_signal_level hsync_level;
+	/* Interlaced or Progressive timings */
+	bool interlace;
 	/* Pixel clock edge to drive LCD data */
 	enum omap_dss_signal_edge data_pclk_edge;
 	/* Data enable logic level */