tree 960d3d6b28b2a6097da4806b1059f55d4fa263ad
parent bbc8d77db655be61a21d7623428c46c578a866d3
author Nicolas Pitre <nicolas.pitre@linaro.org> 1336006612 -0400
committer Nicolas Pitre <nicolas.pitre@linaro.org> 1369857034 -0400

ARM: vexpress: introduce DCSCB support

This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).

The cache coherency interconnect (CCI) is not handled yet.

Signed-off-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>