tree 57c0bc50540ec0f49b7b972f14cee51bc4f22e60
parent 5dbd05d46fb7d849570c8fa09d48591aa7ce1766
author Dimitri Sivanich <sivanich@sgi.com> 1304696024 -0500
committer Dan Williams <dan.j.williams@intel.com> 1306455084 -0700

x86: poll waiting for I/OAT DMA channel status

For certain system configurations a 5 usec udelay before checking I/OAT DMA
channel status is sometimes not sufficient, resulting in a false failure
status and unnecessary freeing of channel resources.  Conversely, for many
configurations 5 usec is longer than necessary.

Loop for up to 20 usec waiting for successful status before failing.

Signed-off-by: Dimitri Sivanich <sivanich@sgi.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>