[PATCH] xtensa: remove extra header files
The Xtensa port contained many header files that were never needed. This
rather lengthy patch removes all those files. Unfortunately, there were
many dependencies that needed to be updated, so this patch touches quite a
few source files.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
diff --git a/arch/xtensa/kernel/align.S b/arch/xtensa/kernel/align.S
index a495657..33d6e9d 100644
--- a/arch/xtensa/kernel/align.S
+++ b/arch/xtensa/kernel/align.S
@@ -16,14 +16,9 @@
*/
#include <linux/linkage.h>
-#include <asm/ptrace.h>
-#include <asm/ptrace.h>
#include <asm/current.h>
#include <asm/asm-offsets.h>
-#include <asm/pgtable.h>
#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/thread_info.h>
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
@@ -216,7 +211,7 @@
extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
-#if XCHAL_HAVE_NARROW
+#if XCHAL_HAVE_DENSITY
_beqi a5, OP0_L32I_N, .Lload # L32I.N, jump
addi a6, a5, -OP0_S32I_N
_beqz a6, .Lstore # S32I.N, do a store
@@ -251,7 +246,7 @@
#endif
__src_b a3, a5, a6 # a3 has the data word
-#if XCHAL_HAVE_NARROW
+#if XCHAL_HAVE_DENSITY
addi a7, a7, 2 # increment PC (assume 16-bit insn)
extui a5, a4, INSN_OP0, 4
@@ -279,14 +274,14 @@
1:
-#if XCHAL_HAVE_LOOP
- rsr a3, LEND # check if we reached LEND
- bne a7, a3, 1f
- rsr a3, LCOUNT # and LCOUNT != 0
- beqz a3, 1f
- addi a3, a3, -1 # decrement LCOUNT and set
+#if XCHAL_HAVE_LOOPS
+ rsr a5, LEND # check if we reached LEND
+ bne a7, a5, 1f
+ rsr a5, LCOUNT # and LCOUNT != 0
+ beqz a5, 1f
+ addi a5, a5, -1 # decrement LCOUNT and set
rsr a7, LBEG # set PC to LBEGIN
- wsr a3, LCOUNT
+ wsr a5, LCOUNT
#endif
1: wsr a7, EPC_1 # skip load instruction
@@ -336,7 +331,7 @@
movi a6, 0 # mask: ffffffff:00000000
-#if XCHAL_HAVE_NARROW
+#if XCHAL_HAVE_DENSITY
addi a7, a7, 2 # incr. PC,assume 16-bit instruction
extui a5, a4, INSN_OP0, 4 # extract OP0
@@ -359,14 +354,14 @@
/* Get memory address */
1:
-#if XCHAL_HAVE_LOOP
- rsr a3, LEND # check if we reached LEND
- bne a7, a3, 1f
- rsr a3, LCOUNT # and LCOUNT != 0
- beqz a3, 1f
- addi a3, a3, -1 # decrement LCOUNT and set
+#if XCHAL_HAVE_LOOPS
+ rsr a4, LEND # check if we reached LEND
+ bne a7, a4, 1f
+ rsr a4, LCOUNT # and LCOUNT != 0
+ beqz a4, 1f
+ addi a4, a4, -1 # decrement LCOUNT and set
rsr a7, LBEG # set PC to LBEGIN
- wsr a3, LCOUNT
+ wsr a4, LCOUNT
#endif
1: wsr a7, EPC_1 # skip store instruction
@@ -416,6 +411,7 @@
/* Restore working register */
+ l32i a8, a2, PT_AREG8
l32i a7, a2, PT_AREG7
l32i a6, a2, PT_AREG6
l32i a5, a2, PT_AREG5
@@ -446,7 +442,7 @@
mov a1, a2
rsr a0, PS
- bbsi.l a2, PS_UM_SHIFT, 1f # jump if user mode
+ bbsi.l a2, PS_UM_BIT, 1f # jump if user mode
movi a0, _kernel_exception
jx a0
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index cf5a93f..01bcb9f 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -90,7 +90,6 @@
rsync
retw
-#endif
ENTRY(save_coprocessor_extra)
entry sp, 16
@@ -197,4 +196,5 @@
XCHAL_CP7_SA_CONTENTS_LIBDB
.word 0xFC000000 /* invalid register number,marks end of table*/
_xtensa_reginfo_table_end:
+#endif
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 89e409e..c0b56b1 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -24,7 +24,7 @@
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/signal.h>
-#include <xtensa/coreasm.h>
+#include <asm/tlbflush.h>
/* Unimplemented features. */
@@ -364,7 +364,7 @@
movi a2, 1
extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
- movi a2, PS_WOE_MASK
+ movi a2, 1 << PS_WOE_BIT
or a3, a3, a2
rsr a0, EXCCAUSE
xsr a3, PS
@@ -399,7 +399,7 @@
/* Jump if we are returning from kernel exceptions. */
1: l32i a3, a1, PT_PS
- _bbsi.l a3, PS_UM_SHIFT, 2f
+ _bbsi.l a3, PS_UM_BIT, 2f
j kernel_exception_exit
/* Specific to a user exception exit:
@@ -422,7 +422,7 @@
* (Hint: There is only one user exception frame on stack)
*/
- movi a3, PS_WOE_MASK
+ movi a3, 1 << PS_WOE_BIT
_bbsi.l a4, TIF_NEED_RESCHED, 3f
_bbci.l a4, TIF_SIGPENDING, 4f
@@ -694,7 +694,7 @@
ENTRY(debug_exception)
rsr a0, EPS + XCHAL_DEBUGLEVEL
- bbsi.l a0, PS_EXCM_SHIFT, 1f # exception mode
+ bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
/* Set EPC_1 and EXCCAUSE */
@@ -707,7 +707,7 @@
/* Restore PS to the value before the debug exc but with PS.EXCM set.*/
- movi a2, 1 << PS_EXCM_SHIFT
+ movi a2, 1 << PS_EXCM_BIT
or a2, a0, a2
movi a0, debug_exception # restore a3, debug jump vector
wsr a2, PS
@@ -715,7 +715,7 @@
/* Switch to kernel/user stack, restore jump vector, and save a0 */
- bbsi.l a2, PS_UM_SHIFT, 2f # jump if user mode
+ bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
addi a2, a1, -16-PT_SIZE # assume kernel stack
s32i a0, a2, PT_AREG0
@@ -778,7 +778,7 @@
wsr a1, WINDOWBASE
rsync
- movi a1, PS_WOE_MASK | 1
+ movi a1, (1 << PS_WOE_BIT) | 1
wsr a1, PS
rsync
@@ -1491,7 +1491,7 @@
*/
rsr a0, PS
- _bbci.l a0, PS_UM_SHIFT, 1f
+ _bbci.l a0, PS_UM_BIT, 1f
/* User space: Setup a dummy frame and kill application.
* Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
@@ -1510,7 +1510,7 @@
l32i a1, a3, EXC_TABLE_KSTK
wsr a3, EXCSAVE_1
- movi a4, PS_WOE_MASK | 1
+ movi a4, (1 << PS_WOE_BIT) | 1
wsr a4, PS
rsync
@@ -1612,7 +1612,7 @@
rsr a1, PTEVADDR
srli a1, a1, PAGE_SHIFT
slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
- addi a1, a1, DTLB_WAY_PGTABLE # ... + way_number
+ addi a1, a1, DTLB_WAY_PGD # ... + way_number
wdtlb a0, a1
dsync
@@ -1654,7 +1654,7 @@
mov a1, a2
rsr a2, PS
- bbsi.l a2, PS_UM_SHIFT, 1f
+ bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
@@ -1753,7 +1753,7 @@
mov a1, a2
rsr a2, PS
- bbsi.l a2, PS_UM_SHIFT, 1f
+ bbsi.l a2, PS_UM_BIT, 1f
j _kernel_exception
1: j _user_exception
@@ -1924,7 +1924,7 @@
/* Disable ints while we manipulate the stack pointer; spill regs. */
- movi a5, PS_EXCM_MASK | LOCKLEVEL
+ movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL
xsr a5, PS
rsr a3, EXCSAVE_1
rsync
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index c07cb25..ea89910 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -15,9 +15,9 @@
* Kevin Chea
*/
-#include <xtensa/cacheasm.h>
#include <asm/processor.h>
#include <asm/page.h>
+#include <asm/cacheasm.h>
/*
* This module contains the entry code for kernel images. It performs the
@@ -32,13 +32,6 @@
*
*/
- .macro iterate from, to , cmd
- .ifeq ((\to - \from) & ~0xfff)
- \cmd \from
- iterate "(\from+1)", \to, \cmd
- .endif
- .endm
-
/*
* _start
*
@@ -64,7 +57,7 @@
/* Disable interrupts and exceptions. */
- movi a0, XCHAL_PS_EXCM_MASK
+ movi a0, LOCKLEVEL
wsr a0, PS
/* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
@@ -91,11 +84,11 @@
movi a1, 15
wsr a0, ICOUNTLEVEL
- .macro reset_dbreak num
- wsr a0, DBREAKC + \num
- .endm
-
- iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak
+ .set _index, 0
+ .rept XCHAL_NUM_DBREAK - 1
+ wsr a0, DBREAKC + _index
+ .set _index, _index + 1
+ .endr
#endif
/* Clear CCOUNT (not really necessary, but nice) */
@@ -110,10 +103,11 @@
/* Disable all timers. */
- .macro reset_timer num
- wsr a0, CCOMPARE_0 + \num
- .endm
- iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
+ .set _index, 0
+ .rept XCHAL_NUM_TIMERS - 1
+ wsr a0, CCOMPARE + _index
+ .set _index, _index + 1
+ .endr
/* Interrupt initialization. */
@@ -139,12 +133,21 @@
rsync
/* Initialize the caches.
- * Does not include flushing writeback d-cache.
- * a6, a7 are just working registers (clobbered).
+ * a2, a3 are just working registers (clobbered).
*/
- icache_reset a2, a3
- dcache_reset a2, a3
+#if XCHAL_DCACHE_LINE_LOCKABLE
+ ___unlock_dcache_all a2 a3
+#endif
+
+#if XCHAL_ICACHE_LINE_LOCKABLE
+ ___unlock_icache_all a2 a3
+#endif
+
+ ___invalidate_dcache_all a2 a3
+ ___invalidate_icache_all a2 a3
+
+ isync
/* Unpack data sections
*
@@ -181,9 +184,9 @@
movi a2, _bss_start # start of BSS
movi a3, _bss_end # end of BSS
-1: addi a2, a2, 4
+ __loopt a2, a3, a4, 2
s32i a0, a2, 0
- blt a2, a3, 1b
+ __endla a2, a4, 4
#if XCHAL_DCACHE_IS_WRITEBACK
@@ -191,7 +194,7 @@
* instructions/data are available.
*/
- dcache_writeback_all a2, a3
+ ___flush_dcache_all a2 a3
#endif
/* Setup stack and enable window exceptions (keep irqs disabled) */
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index 6648fa9..ca76f07 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -1,5 +1,5 @@
/*
- * arch/xtensa/kernel/pci-dma.c
+ * arch/xtensa/pci-dma.c
*
* DMA coherent memory allocation.
*
@@ -29,28 +29,48 @@
*/
void *
-dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp)
+dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag)
{
- void *ret;
+ unsigned long ret;
+ unsigned long uncached = 0;
/* ignore region speicifiers */
- gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
- if (dev == NULL || (*dev->dma_mask < 0xffffffff))
- gfp |= GFP_DMA;
- ret = (void *)__get_free_pages(gfp, get_order(size));
+ flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
- if (ret != NULL) {
- memset(ret, 0, size);
- *handle = virt_to_bus(ret);
+ if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
+ flag |= GFP_DMA;
+ ret = (unsigned long)__get_free_pages(flag, get_order(size));
+
+ if (ret == 0)
+ return NULL;
+
+ /* We currently don't support coherent memory outside KSEG */
+
+ if (ret < XCHAL_KSEG_CACHED_VADDR
+ || ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE)
+ BUG();
+
+
+ if (ret != 0) {
+ memset((void*) ret, 0, size);
+ uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR;
+ *handle = virt_to_bus((void*)ret);
+ __flush_invalidate_dcache_range(ret, size);
}
- return (void*) BYPASS_ADDR((unsigned long)ret);
+
+ return (void*)uncached;
}
void dma_free_coherent(struct device *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
- free_pages(CACHED_ADDR((unsigned long)vaddr), get_order(size));
+ long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR;
+
+ if (addr < 0 || addr >= XCHAL_KSEG_SIZE)
+ BUG();
+
+ free_pages(addr, get_order(size));
}
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c
index a7c4178..3785f34 100644
--- a/arch/xtensa/kernel/process.c
+++ b/arch/xtensa/kernel/process.c
@@ -1,4 +1,3 @@
-// TODO verify coprocessor handling
/*
* arch/xtensa/kernel/process.c
*
@@ -43,7 +42,7 @@
#include <asm/irq.h>
#include <asm/atomic.h>
#include <asm/asm-offsets.h>
-#include <asm/coprocessor.h>
+#include <asm/regs.h>
extern void ret_from_fork(void);
@@ -67,25 +66,6 @@
EXPORT_SYMBOL(pm_power_off);
-#if XCHAL_CP_NUM > 0
-
-/*
- * Coprocessor ownership.
- */
-
-coprocessor_info_t coprocessor_info[] = {
- { 0, XTENSA_CPE_CP0_OFFSET },
- { 0, XTENSA_CPE_CP1_OFFSET },
- { 0, XTENSA_CPE_CP2_OFFSET },
- { 0, XTENSA_CPE_CP3_OFFSET },
- { 0, XTENSA_CPE_CP4_OFFSET },
- { 0, XTENSA_CPE_CP5_OFFSET },
- { 0, XTENSA_CPE_CP6_OFFSET },
- { 0, XTENSA_CPE_CP7_OFFSET },
-};
-
-#endif
-
/*
* Powermanagement idle function, if any is provided by the platform.
*/
@@ -110,12 +90,10 @@
void exit_thread(void)
{
- release_coprocessors(current); /* Empty macro if no CPs are defined */
}
void flush_thread(void)
{
- release_coprocessors(current); /* Empty macro if no CPs are defined */
}
/*
@@ -275,7 +253,7 @@
*/
elfregs->pc = regs->pc;
- elfregs->ps = (regs->ps & ~XCHAL_PS_EXCM_MASK);
+ elfregs->ps = (regs->ps & ~(1 << PS_EXCM_BIT));
elfregs->exccause = regs->exccause;
elfregs->excvaddr = regs->excvaddr;
elfregs->windowbase = regs->windowbase;
@@ -325,7 +303,7 @@
*/
regs->pc = elfregs->pc;
- regs->ps = (elfregs->ps | XCHAL_PS_EXCM_MASK);
+ regs->ps = (elfregs->ps | (1 << PS_EXCM_BIT));
regs->exccause = elfregs->exccause;
regs->excvaddr = elfregs->excvaddr;
regs->windowbase = elfregs->windowbase;
@@ -459,16 +437,7 @@
int
dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r)
{
-/* see asm/coprocessor.h for this magic number 16 */
-#if XTENSA_CP_EXTRA_SIZE > 16
- do_save_fpregs (r, regs, task);
-
- /* For now, bit 16 means some extra state may be present: */
-// FIXME!! need to track to return more accurate mask
- return 0x10000 | XCHAL_CP_MASK;
-#else
return 0; /* no coprocessors active on this processor */
-#endif
}
/*
diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c
index 9aea23c..604c3c3c 100644
--- a/arch/xtensa/kernel/ptrace.c
+++ b/arch/xtensa/kernel/ptrace.c
@@ -96,7 +96,7 @@
/* Note: PS.EXCM is not set while user task is running;
* its being set in regs is for exception handling
* convenience. */
- tmp = (regs->ps & ~XCHAL_PS_EXCM_MASK);
+ tmp = (regs->ps & ~(1 << PS_EXCM_BIT));
break;
case REG_WB:
tmp = regs->windowbase;
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index c99ab72..b6374c0 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -42,8 +42,6 @@
#include <asm/page.h>
#include <asm/setup.h>
-#include <xtensa/config/system.h>
-
#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
#endif
@@ -336,7 +334,7 @@
/* high-level stuff */
seq_printf(f,"processor\t: 0\n"
"vendor_id\t: Tensilica\n"
- "model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n"
+ "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
"core ID\t\t: " XCHAL_CORE_ID "\n"
"build ID\t: 0x%x\n"
"byte order\t: %s\n"
@@ -420,25 +418,6 @@
XCHAL_NUM_TIMERS,
XCHAL_DEBUGLEVEL);
- /* Coprocessors */
-#if XCHAL_HAVE_CP
- seq_printf(f, "coprocessors\t: %d\n", XCHAL_CP_NUM);
-#else
- seq_printf(f, "coprocessors\t: none\n");
-#endif
-
- /* {I,D}{RAM,ROM} and XLMI */
- seq_printf(f,"inst ROMs\t: %d\n"
- "inst RAMs\t: %d\n"
- "data ROMs\t: %d\n"
- "data RAMs\t: %d\n"
- "XLMI ports\t: %d\n",
- XCHAL_NUM_IROM,
- XCHAL_NUM_IRAM,
- XCHAL_NUM_DROM,
- XCHAL_NUM_DRAM,
- XCHAL_NUM_XLMI);
-
/* Cache */
seq_printf(f,"icache line size: %d\n"
"icache ways\t: %d\n"
@@ -466,24 +445,6 @@
XCHAL_DCACHE_WAYS,
XCHAL_DCACHE_SIZE);
- /* MMU */
- seq_printf(f,"ASID bits\t: %d\n"
- "ASID invalid\t: %d\n"
- "ASID kernel\t: %d\n"
- "rings\t\t: %d\n"
- "itlb ways\t: %d\n"
- "itlb AR ways\t: %d\n"
- "dtlb ways\t: %d\n"
- "dtlb AR ways\t: %d\n",
- XCHAL_MMU_ASID_BITS,
- XCHAL_MMU_ASID_INVALID,
- XCHAL_MMU_ASID_KERNEL,
- XCHAL_MMU_RINGS,
- XCHAL_ITLB_WAYS,
- XCHAL_ITLB_ARF_WAYS,
- XCHAL_DTLB_WAYS,
- XCHAL_DTLB_ARF_WAYS);
-
return 0;
}
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index c494f08..6af7f41 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -12,8 +12,8 @@
*
*/
-#include <xtensa/config/core.h>
-#include <xtensa/hal.h>
+#include <asm/variant/core.h>
+#include <asm/coprocessor.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/smp.h>
@@ -216,8 +216,8 @@
* handler, or the user mode value doesn't matter (e.g. PS.OWB).
*/
err |= __get_user(ps, &sc->sc_ps);
- regs->ps = (regs->ps & ~XCHAL_PS_CALLINC_MASK)
- | (ps & XCHAL_PS_CALLINC_MASK);
+ regs->ps = (regs->ps & ~PS_CALLINC_MASK)
+ | (ps & PS_CALLINC_MASK);
/* Additional corruption checks */
@@ -280,7 +280,7 @@
static int
save_cpextra (struct _cpstate *buf)
{
-#if (XCHAL_EXTRA_SA_SIZE == 0) && (XCHAL_CP_NUM == 0)
+#if XCHAL_CP_NUM == 0
return 0;
#else
@@ -497,8 +497,10 @@
/* Flush generated code out of the data cache */
- if (err == 0)
- __flush_invalidate_cache_range((unsigned long)codemem, 6UL);
+ if (err == 0) {
+ __invalidate_icache_range((unsigned long)codemem, 6UL);
+ __flush_invalidate_dcache_range((unsigned long)codemem, 6UL);
+ }
return err;
}
diff --git a/arch/xtensa/kernel/syscalls.c b/arch/xtensa/kernel/syscalls.c
index f49cb23..f9a5a75 100644
--- a/arch/xtensa/kernel/syscalls.c
+++ b/arch/xtensa/kernel/syscalls.c
@@ -175,8 +175,8 @@
* interrupts in the first place:
*/
local_save_flags (ps);
- local_irq_restore((ps & ~XCHAL_PS_INTLEVEL_MASK) |
- (regs->ps & XCHAL_PS_INTLEVEL_MASK) );
+ local_irq_restore((ps & ~PS_INTLEVEL_MASK) |
+ (regs->ps & PS_INTLEVEL_MASK) );
if (syscallnr > __NR_Linux_syscalls) {
regs->areg[2] = -ENOSYS;
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index ce077d6..693ab26 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -75,7 +75,7 @@
#define USER 0x02
#define COPROCESSOR(x) \
-{ XCHAL_EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor }
+{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor }
typedef struct {
int cause;
@@ -85,38 +85,38 @@
dispatch_init_table_t __init dispatch_init_table[] = {
-{ XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction},
-{ XCHAL_EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel },
-{ XCHAL_EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user },
-{ XCHAL_EXCCAUSE_SYSTEM_CALL, 0, system_call },
-/* XCHAL_EXCCAUSE_INSTRUCTION_FETCH unhandled */
-/* XCHAL_EXCCAUSE_LOAD_STORE_ERROR unhandled*/
-{ XCHAL_EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt },
-{ XCHAL_EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca },
-/* XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */
-/* XCHAL_EXCCAUSE_PRIVILEGED unhandled */
+{ EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction},
+{ EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel },
+{ EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user },
+{ EXCCAUSE_SYSTEM_CALL, 0, system_call },
+/* EXCCAUSE_INSTRUCTION_FETCH unhandled */
+/* EXCCAUSE_LOAD_STORE_ERROR unhandled*/
+{ EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt },
+{ EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca },
+/* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */
+/* EXCCAUSE_PRIVILEGED unhandled */
#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
#ifdef CONFIG_UNALIGNED_USER
-{ XCHAL_EXCCAUSE_UNALIGNED, USER, fast_unaligned },
+{ EXCCAUSE_UNALIGNED, USER, fast_unaligned },
#else
-{ XCHAL_EXCCAUSE_UNALIGNED, 0, do_unaligned_user },
+{ EXCCAUSE_UNALIGNED, 0, do_unaligned_user },
#endif
-{ XCHAL_EXCCAUSE_UNALIGNED, KRNL, fast_unaligned },
+{ EXCCAUSE_UNALIGNED, KRNL, fast_unaligned },
#endif
-{ XCHAL_EXCCAUSE_ITLB_MISS, 0, do_page_fault },
-{ XCHAL_EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss},
-{ XCHAL_EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit },
-{ XCHAL_EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault },
-/* XCHAL_EXCCAUSE_SIZE_RESTRICTION unhandled */
-{ XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault },
-{ XCHAL_EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss},
-{ XCHAL_EXCCAUSE_DTLB_MISS, 0, do_page_fault },
-{ XCHAL_EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit },
-{ XCHAL_EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault },
-/* XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */
-{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited },
-{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault },
-{ XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault },
+{ EXCCAUSE_ITLB_MISS, 0, do_page_fault },
+{ EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss},
+{ EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit },
+{ EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault },
+/* EXCCAUSE_SIZE_RESTRICTION unhandled */
+{ EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault },
+{ EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss},
+{ EXCCAUSE_DTLB_MISS, 0, do_page_fault },
+{ EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit },
+{ EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault },
+/* EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */
+{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited },
+{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault },
+{ EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault },
/* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */
#if (XCHAL_CP_MASK & 1)
COPROCESSOR(0),
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index 0e74397..eb2d7bb 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -53,6 +53,8 @@
#include <asm/thread_info.h>
#include <asm/processor.h>
+#define WINDOW_VECTORS_SIZE 0x180
+
/*
* User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0)
@@ -210,7 +212,7 @@
/* Check for kernel double exception (usually fatal). */
rsr a3, PS
- _bbci.l a3, PS_UM_SHIFT, .Lksp
+ _bbci.l a3, PS_UM_BIT, .Lksp
/* Check if we are currently handling a window exception. */
/* Note: We don't need to indicate that we enter a critical section. */
@@ -219,7 +221,7 @@
movi a3, XCHAL_WINDOW_VECTORS_VADDR
_bltu a0, a3, .Lfixup
- addi a3, a3, XSHAL_WINDOW_VECTORS_SIZE
+ addi a3, a3, WINDOW_VECTORS_SIZE
_bgeu a0, a3, .Lfixup
/* Window overflow/underflow exception. Get stack pointer. */
@@ -245,7 +247,7 @@
wsr a2, DEPC # save stack pointer temporarily
rsr a0, PS
- extui a0, a0, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
+ extui a0, a0, PS_OWB_SHIFT, 4
wsr a0, WINDOWBASE
rsync
@@ -312,8 +314,8 @@
.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */
rsr a3, EXCCAUSE
- beqi a3, XCHAL_EXCCAUSE_ITLB_MISS, 1f
- addi a3, a3, -XCHAL_EXCCAUSE_DTLB_MISS
+ beqi a3, EXCCAUSE_ITLB_MISS, 1f
+ addi a3, a3, -EXCCAUSE_DTLB_MISS
bnez a3, .Lunrecoverable
1: movi a3, fast_second_level_miss_double_kernel
jx a3
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index e01131f..a36c104 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -16,20 +16,17 @@
#include <asm-generic/vmlinux.lds.h>
-#define _NOCLANGUAGE
-#undef __ASSEMBLER__
-#include <xtensa/config/core.h>
-#include <xtensa/config/system.h>
+#include <asm/variant/core.h>
OUTPUT_ARCH(xtensa)
ENTRY(_start)
-#if XCHAL_MEMORY_ORDER == XTHAL_BIGENDIAN
+#ifdef __XTENSA_EB__
jiffies = jiffies_64 + 4;
#else
jiffies = jiffies_64;
#endif
-#define KERNELOFFSET 0x1000
+#define KERNELOFFSET 0xd0001000
/* Note: In the following macros, it would be nice to specify only the
vector name and section kind and construct "sym" and "section" using
@@ -76,7 +73,7 @@
SECTIONS
{
- . = XCHAL_KSEG_CACHED_VADDR + KERNELOFFSET;
+ . = KERNELOFFSET;
/* .text section */
_text = .;
@@ -160,7 +157,7 @@
/* Initialization code and data: */
- . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE);
+ . = ALIGN(1 << 12);
__init_begin = .;
.init.text : {
_sinittext = .;
@@ -224,32 +221,32 @@
.dummy)
SECTION_VECTOR (_DebugInterruptVector_literal,
.DebugInterruptVector.literal,
- XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) - 4,
+ XCHAL_DEBUG_VECTOR_VADDR - 4,
SIZEOF(.WindowVectors.text),
.WindowVectors.text)
SECTION_VECTOR (_DebugInterruptVector_text,
.DebugInterruptVector.text,
- XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL),
+ XCHAL_DEBUG_VECTOR_VADDR,
4,
.DebugInterruptVector.literal)
SECTION_VECTOR (_KernelExceptionVector_literal,
.KernelExceptionVector.literal,
- XCHAL_KERNELEXC_VECTOR_VADDR - 4,
+ XCHAL_KERNEL_VECTOR_VADDR - 4,
SIZEOF(.DebugInterruptVector.text),
.DebugInterruptVector.text)
SECTION_VECTOR (_KernelExceptionVector_text,
.KernelExceptionVector.text,
- XCHAL_KERNELEXC_VECTOR_VADDR,
+ XCHAL_KERNEL_VECTOR_VADDR,
4,
.KernelExceptionVector.literal)
SECTION_VECTOR (_UserExceptionVector_literal,
.UserExceptionVector.literal,
- XCHAL_USEREXC_VECTOR_VADDR - 4,
+ XCHAL_USER_VECTOR_VADDR - 4,
SIZEOF(.KernelExceptionVector.text),
.KernelExceptionVector.text)
SECTION_VECTOR (_UserExceptionVector_text,
.UserExceptionVector.text,
- XCHAL_USEREXC_VECTOR_VADDR,
+ XCHAL_USER_VECTOR_VADDR,
4,
.UserExceptionVector.literal)
SECTION_VECTOR (_DoubleExceptionVector_literal,
@@ -264,7 +261,7 @@
.DoubleExceptionVector.literal)
. = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;
- . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE);
+ . = ALIGN(1 << 12);
__init_end = .;