| commit | a330b6f5d1aee83fb2554d00ad33877b91a74c0c | [log] [tgz] |
|---|---|---|
| author | Alexey Firago <alexey_firago@mentor.com> | Fri Apr 07 12:12:23 2017 +0300 |
| committer | Stephen Boyd <sboyd@codeaurora.org> | Wed Apr 19 09:08:48 2017 -0700 |
| tree | 9d5288e5e49b7cd9a346cd12f01a2422ae3437af | |
| parent | 9adddb01ce5f71ae5c26b8aff01335d40be55133 [diff] |
clk: vc5: Add bindings for IDT VersaClock 5P49V5935 IDT VersaClock 5 5P49V5935 has 4 clock outputs, 4 fractional dividers. Input clock source can be taken from either integrated crystal or from external reference clock. Signed-off-by: Alexey Firago <alexey_firago@mentor.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>