[ARM] gic: Fix gic cascade irq handling
No need for the cascade irq function to have a "fastcall" annotation.
Fix the range checking for valid IRQ numbers - comparing the value
returned by the GIC with NR_IRQS is meaningless since we translate
the GIC irq number to a Linux IRQ number afterwards.
Check the GIC returned IRQ number is within limits first, then add
the IRQ offset, and only then compare with NR_IRQS.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 4deece5..2ae0bd1 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -125,12 +125,11 @@
}
#endif
-static void fastcall gic_handle_cascade_irq(unsigned int irq,
- struct irq_desc *desc)
+static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{
struct gic_chip_data *chip_data = get_irq_data(irq);
struct irq_chip *chip = get_irq_chip(irq);
- unsigned int cascade_irq;
+ unsigned int cascade_irq, gic_irq;
unsigned long status;
/* primary controller ack'ing */
@@ -140,16 +139,15 @@
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
- cascade_irq = (status & 0x3ff);
- if (cascade_irq > 1020)
+ gic_irq = (status & 0x3ff);
+ if (gic_irq == 1023)
goto out;
- if (cascade_irq < 32 || cascade_irq >= NR_IRQS) {
- do_bad_IRQ(cascade_irq, desc);
- goto out;
- }
- cascade_irq += chip_data->irq_offset;
- generic_handle_irq(cascade_irq);
+ cascade_irq = gic_irq + chip_data->irq_offset;
+ if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
+ do_bad_IRQ(cascade_irq, desc);
+ else
+ generic_handle_irq(cascade_irq);
out:
/* primary controller unmasking */