tree 8367cd4cb3dd7fd7e5c01c2b6117755c6e9ea72e
parent 95bfea1675c02d83cf1923272e62f91db11cbb8f
author Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> 1310604758 +0900
committer Vinod Koul <vinod.koul@intel.com> 1311601272 +0530

pch_dma: Fix CTL register access issue

Currently, Mode-Control register is accessed by read-modify-write.

According to DMA hardware specifications datasheet, prohibits this method.
Because this register resets to 0 by DMA HW after DMA transfer completes.
Thus, current read-modify-write processing can cause unexpected behavior.

The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
e.g. Set DMA0=01b  DMA11=10b
CTL0=33333331h
CTL2=00002333h

NOTE:
CTL0 includes DMA0~7 Mode-Control register.
CTL2 includes DMA8~11 Mode-Control register.

This patch modifies the issue.

Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>