ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs
When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index cd15669..f9119a6 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -519,7 +519,7 @@
dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
reg = wm8993_read(codec, WM8993_CLOCKING_2);
- reg &= ~WM8993_SYSCLK_SRC;
+ reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
if (wm8993->mclk_rate > 13500000) {
reg |= WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate / 2;
@@ -527,8 +527,6 @@
reg &= ~WM8993_MCLK_DIV;
wm8993->sysclk_rate = wm8993->mclk_rate;
}
- reg &= ~WM8993_MCLK_DIV;
- reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
wm8993_write(codec, WM8993_CLOCKING_2, reg);
break;