| commit | cdce35460f5bd929cbcb75a8f436776bd0112f49 | [log] [tgz] |
|---|---|---|
| author | Chao Xie <chao.xie@marvell.com> | Fri Oct 31 10:13:46 2014 +0800 |
| committer | Michael Turquette <mturquette@linaro.org> | Wed Nov 12 16:34:00 2014 -0800 |
| tree | 00f8559dd38991327e643c86701c83faf5ceff4c | |
| parent | ee81f4ee2a3632a2d7928f680c4af8243a18762f [diff] |
clk: mmp: add mmp private gate clock Some SOCes have this kind of the gate clock 1. There are some bits to control the gate not only one bit. 2. It is not always that "1" is to enable while "0" is to disable when write register. So we have to define the "mask", "enable_val", "disable_val" for this kind of gate clock. Signed-off-by: Chao Xie <chao.xie@marvell.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>