ARM: l2c: ux500: don't try to change the L2 cache auxiliary control register
ux500 can't change the auxiliary control register, so there's no point
passing values to try and modify it to the l2x0 init functions.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 5b891d0..842ebed 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -57,9 +57,9 @@
outer_cache.write_sec = ux500_l2c310_write_sec;
if (of_have_populated_dt())
- l2x0_of_init(0x3e000000, 0xc00f0fff);
+ l2x0_of_init(0, ~0);
else
- l2x0_init(l2x0_base, 0x3e000000, 0xc00f0fff);
+ l2x0_init(l2x0_base, 0, ~0);
return 0;
}