tree 76f17bf026fb785fedf86b5ad69dfdf477f94719
parent c9b870e7e796eea515a261a314917317ebb1cb4a
author Byungho Min <bhminjames@gmail.com> 1245760796 +0900
committer Ben Dooks <ben-linux@fluff.org> 1250461500 +0100

ARM: S5PC100: Clock and PLL support

S5PC100 has 4 PLLs (APLL,MPLL,EPLL,HPLL) and 3 clock domains. Clock scheme is
implemented here.

Signed-off-by: Byungho Min <bhmin@samsung.com>
[ben-linux@fluff.org: edited title]
Signed-off-by: Ben Dooks <ben-linux@fluff.org>