ARM: pm: arrange for cpu_proc_init() to be called on resume
cpu_proc_init() does processor specific initialization, which we do
at boot time. We have been omitting to do this on resume, which
causes some of this initialization to be skipped. We've also been
skipping this on SMP initialization too.
Ensure that cpu_proc_init() is always called appropriately by
moving it into cpu_init(), and move cpu_init() to a more appropriate
point in the boot initialization.
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ed11fb0..edcab02 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -342,6 +342,59 @@
elf_hwcap &= ~HWCAP_TLS;
}
+/*
+ * cpu_init - initialise one CPU.
+ *
+ * cpu_init sets up the per-CPU stacks.
+ */
+void cpu_init(void)
+{
+ unsigned int cpu = smp_processor_id();
+ struct stack *stk = &stacks[cpu];
+
+ if (cpu >= NR_CPUS) {
+ printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
+ BUG();
+ }
+
+ cpu_proc_init();
+
+ /*
+ * Define the placement constraint for the inline asm directive below.
+ * In Thumb-2, msr with an immediate value is not allowed.
+ */
+#ifdef CONFIG_THUMB2_KERNEL
+#define PLC "r"
+#else
+#define PLC "I"
+#endif
+
+ /*
+ * setup stacks for re-entrant exception handlers
+ */
+ __asm__ (
+ "msr cpsr_c, %1\n\t"
+ "add r14, %0, %2\n\t"
+ "mov sp, r14\n\t"
+ "msr cpsr_c, %3\n\t"
+ "add r14, %0, %4\n\t"
+ "mov sp, r14\n\t"
+ "msr cpsr_c, %5\n\t"
+ "add r14, %0, %6\n\t"
+ "mov sp, r14\n\t"
+ "msr cpsr_c, %7"
+ :
+ : "r" (stk),
+ PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+ "I" (offsetof(struct stack, irq[0])),
+ PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+ "I" (offsetof(struct stack, abt[0])),
+ PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+ "I" (offsetof(struct stack, und[0])),
+ PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+ : "r14");
+}
+
static void __init setup_processor(void)
{
struct proc_info_list *list;
@@ -387,58 +440,7 @@
feat_v6_fixup();
cacheid_init();
- cpu_proc_init();
-}
-
-/*
- * cpu_init - initialise one CPU.
- *
- * cpu_init sets up the per-CPU stacks.
- */
-void cpu_init(void)
-{
- unsigned int cpu = smp_processor_id();
- struct stack *stk = &stacks[cpu];
-
- if (cpu >= NR_CPUS) {
- printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
- BUG();
- }
-
- /*
- * Define the placement constraint for the inline asm directive below.
- * In Thumb-2, msr with an immediate value is not allowed.
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define PLC "r"
-#else
-#define PLC "I"
-#endif
-
- /*
- * setup stacks for re-entrant exception handlers
- */
- __asm__ (
- "msr cpsr_c, %1\n\t"
- "add r14, %0, %2\n\t"
- "mov sp, r14\n\t"
- "msr cpsr_c, %3\n\t"
- "add r14, %0, %4\n\t"
- "mov sp, r14\n\t"
- "msr cpsr_c, %5\n\t"
- "add r14, %0, %6\n\t"
- "mov sp, r14\n\t"
- "msr cpsr_c, %7"
- :
- : "r" (stk),
- PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
- "I" (offsetof(struct stack, irq[0])),
- PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
- "I" (offsetof(struct stack, abt[0])),
- PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
- "I" (offsetof(struct stack, und[0])),
- PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
- : "r14");
+ cpu_init();
}
void __init dump_machine_table(void)
@@ -913,7 +915,6 @@
#endif
reserve_crashkernel();
- cpu_init();
tcm_init();
#ifdef CONFIG_MULTI_IRQ_HANDLER