/*
 * Copyright (c) 2018 Samsung Electronics Co., Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Common Clock Framework support for Exynos9820 SoC.
 */

#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <soc/samsung/cal-if.h>
#include <dt-bindings/clock/exynos9820.h>

#include "../../soc/samsung/cal-if/exynos9820/cmucal-vclk.h"
#include "../../soc/samsung/cal-if/exynos9820/cmucal-node.h"
#include "../../soc/samsung/cal-if/exynos9820/cmucal-qch.h"
#include "../../soc/samsung/cal-if/exynos9820/clkout_exynos9820.h"
#include "composite.h"

static struct samsung_clk_provider *exynos9820_clk_provider;
/*
 * list of controller registers to be saved and restored during a
 * suspend/resume cycle.
 */
/* fixed rate clocks generated outside the soc */
struct samsung_fixed_rate exynos9820_fixed_rate_ext_clks[] __initdata = {
	FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000),
};

/* HWACG VCLK */
struct init_vclk exynos9820_apm_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_DLL, MUX_DLL_USER, "UMUX_DLL", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKMUX_APM_RCO, MUX_CLKMUX_APM_RCO_USER, "UMUX_CLKMUX_APM_RCO", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_GREBEINTEGRATION_GREBE, GREBEINTEGRATION_QCH_GREBE, "GATE_GREBEINTEGRATION_GREBE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GREBEINTEGRATION_DBG, GREBEINTEGRATION_QCH_DBG, "GATE_GREBEINTEGRATION_DBG", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GREBEINTEGRATION_DBGCORE_GREBE, GREBEINTEGRATION_DBGCORE_QCH_GREBE, "GATE_GREBEINTEGRATION_DBGCORE_GREBE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GREBEINTEGRATION_DBGCORE_DBG, GREBEINTEGRATION_DBGCORE_QCH_DBG, "GATE_GREBEINTEGRATION_DBGCORE_DBG", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_INTMEM, INTMEM_QCH, "GATE_INTMEM_QCH", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM_AP, MAILBOX_APM_AP_QCH, "GATE_MAILBOX_APM_AP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM_CP, MAILBOX_APM_CP_QCH, "GATE_MAILBOX_APM_CP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_APM_VTS, MAILBOX_APM_VTS_QCH, "GATE_MAILBOX_APM_VTS", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_AP_CP, MAILBOX_AP_CP_QCH, "GATE_MAILBOX_AP_CP", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_AP_CP_S, MAILBOX_AP_CP_S_QCH, "GATE_MAILBOX_AP_CP_S", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_AP_DBGCORE, MAILBOX_AP_DBGCORE_QCH, "GATE_MAILBOX_AP_DBGCORE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PEM, PEM_QCH, "GATE_PEM_QCH", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PMU_INTR_GEN, PMU_INTR_GEN_QCH, "GATE_PMU_INTR_GEN", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_RSTNSYNC_CLK_APM_BUS_GREBE, RSTNSYNC_CLK_APM_BUS_QCH_GREBE, "GATE_RSTNSYNC_CLK_APM_BUS_GREBE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_RSTNSYNC_CLK_APM_BUS_GREBE_DBG, RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG, "GATE_RSTNSYNC_CLK_APM_BUS_GREBE_DBG", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_APM, SPEEDY_APM_QCH, "GATE_SPEEDY_APM", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPEEDY_SUB_APM, SPEEDY_SUB_APM_QCH, "GATE_SPEEDY_SUB_APM", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_APM, SYSREG_APM_QCH, "GATE_SYSREG_APM", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_APM, WDT_APM_QCH, "GATE_WDT_APM", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_abox_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_ABOX_ACLK, ABOX_QCH_ACLK, "GATE_ABOX_ACLK", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BCLK_DSIF, ABOX_QCH_BCLK_DSIF, "GATE_ABOX_BCLK_DSIF", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BCLK0, ABOX_QCH_BCLK0, "GATE_ABOX_BCLK0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BCLK1, ABOX_QCH_BCLK1, "GATE_ABOX_BCLK1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BCLK2, ABOX_QCH_BCLK2, "GATE_ABOX_BCLK2", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_BCLK3, ABOX_QCH_BCLK3, "GATE_ABOX_BCLK3", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ABOX_CNT, ABOX_QCH_CNT, "GATE_ABOX_CNT", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_AUD_CMU_AUD, AUD_CMU_AUD_QCH, "GATE_AUD_CMU_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_BTM_AUD, BTM_AUD_QCH, "GATE_BTM_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_AUD, DFTMUX_AUD_QCH, "GATE_DFTMUX_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC, DMIC_QCH, "GATE_DMIC", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_AUD, GPIO_AUD_QCH, "GATE_GPIO_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PPMU_AUD, PPMU_AUD_QCH, "GATE_PPMU_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_AUD, SMMU_AUD_QCH, "GATE_SMMU_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_AUD, SYSREG_AUD_QCH, "GATE_SYSREG_AUD", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_AUD, WDT_AUD_QCH, "GATE_WDT_AUD", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_busc_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_BUSC_BUS, MUX_CLKCMU_BUSC_BUS, "UMUX_CLKCMU_BUSC_BUS", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_MMCACHE, MMCACHE_QCH, "GATE_MMCACHE", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PDMA0, PDMA0_QCH, "GATE_PDMA0", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PPFW, PPFW_QCH, "GATE_PPFW", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SBIC, SBIC_QCH, "GATE_SBIC", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SIREX, SIREX_QCH, "GATE_SIREX", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPDMA, SPDMA_QCH, "GATE_SPDMA", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_BUSC, SYSREG_BUSC_QCH, "GATE_SYSREG_BUSC", "UMUX_CLKCMU_BUSC_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_cmgp_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_CMGP_BUS, MUX_CLKCMU_CMGP_BUS_USER, "UMUX_CLKCMU_CMGP_BUS", NULL, 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_ADC_CMGP_S0, ADC_CMGP_QCH_S0, "GATE_ADC_CMGP_S0", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_ADC_CMGP_S1, ADC_CMGP_QCH_S1, "GATE_ADC_CMGP_S1", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_CMGP_CMU_CMGP, CMGP_CMU_CMGP_QCH, "GATE_CMGP_CMU_CMGP", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_CMGP, GPIO_CMGP_QCH, "GATE_GPIO_CMGP", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CMGP0, I2C_CMGP0_QCH, "GATE_I2C_CMGP0", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CMGP1, I2C_CMGP1_QCH, "GATE_I2C_CMGP1", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CMGP2, I2C_CMGP2_QCH, "GATE_I2C_CMGP2", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CMGP3, I2C_CMGP3_QCH, "GATE_I2C_CMGP3", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_CMGP, SYSREG_CMGP_QCH, "GATE_SYSREG_CMGP", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_CMGP2APM, SYSREG_CMGP2APM_QCH, "GATE_SYSREG_CMGP2APM", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_CMGP2CP, SYSREG_CMGP2CP_QCH, "GATE_SYSREG_CMGP2CP", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_CMGP2PMU_AP, SYSREG_CMGP2PMU_AP_QCH, "GATE_SYSREG_CMGP2PMU_AP", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI_CMGP0, USI_CMGP0_QCH, "GATE_USI_CMGP0", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI_CMGP1, USI_CMGP1_QCH, "GATE_USI_CMGP1", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI_CMGP2, USI_CMGP2_QCH, "GATE_USI_CMGP2", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI_CMGP3, USI_CMGP3_QCH, "GATE_USI_CMGP3", "UMUX_CLKCMU_CMGP_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_cmu_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_CMU_CMU_CMUREF, CMU_CMU_CMUREF_QCH, "GATE_CMU_CMU_CMUREF", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK0, DFTMUX_TOP_QCH_CIS_CLK0, "GATE_DFTMUX_TOP_QCH_CIS_CLK0", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK1, DFTMUX_TOP_QCH_CIS_CLK1, "GATE_DFTMUX_TOP_QCH_CIS_CLK1", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK2, DFTMUX_TOP_QCH_CIS_CLK2, "GATE_DFTMUX_TOP_QCH_CIS_CLK2", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK3, DFTMUX_TOP_QCH_CIS_CLK3, "GATE_DFTMUX_TOP_QCH_CIS_CLK3", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_DFTMUX_TOP_CIS_CLK4, DFTMUX_TOP_QCH_CIS_CLK4, "GATE_DFTMUX_TOP_QCH_CIS_CLK4", NULL, 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_OTP, OTP_QCH, "GATE_OTP", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_core_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_TREX_D_CORE, TREX_D_CORE_QCH, "GATE_TREX_D_CORE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TREX_P0_CORE, TREX_P0_CORE_QCH, "GATE_TREX_P0_CORE", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TREX_P1_CORE, TREX_P1_CORE_QCH, "GATE_TREX_P1_CORE", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_dpu_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DPU_BUS, MUX_CLKCMU_DPU_BUS_USER, "UMUX_CLKCMU_DPU_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_DPU_DPU, DPU_QCH_DPU, "GATE_DPU_QCH_DPU", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DPU_DMA, DPU_QCH_DPU_DMA, "GATE_DPU_QCH_DPU_DMA", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DPU_DPP, DPU_QCH_DPU_DPP, "GATE_DPU_QCH_DPU_DPP", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_DPU_WB_MUX, DPU_QCH_DPU_WB_MUX, "GATE_DPU_QCH_DPU_WB_MUX", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DPU_CMU_DPU, DPU_CMU_DPU_QCH, "GATE_DPU_CMU_DPU", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DPUD0, SYSMMU_DPUD0_QCH, "GATE_SYSMMU_DPUD0", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DPUD1, SYSMMU_DPUD1_QCH, "GATE_SYSMMU_DPUD1", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DPUD2, SYSMMU_DPUD2_QCH, "GATE_SYSMMU_DPUD2", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_DPU, SYSREG_DPU_QCH, "GATE_SYSREG_DPU", "UMUX_CLKCMU_DPU_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_dspm_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DSPM_BUS, MUX_CLKCMU_DSPM_BUS_USER, "UMUX_CLKCMU_DSPM_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_DSPM_BUS_OTF, MUX_CLKCMU_DSPM_BUS_OTF_USER, "UMUX_CLKCMU_DSPM_BUS_OTF", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_SCORE_TS_II, SCORE_TS_II_QCH, "GATE_SCORE_TS_II", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DSPM0, SYSMMU_DSPM0_QCH, "GATE_SYSMMU_DSPM0", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_DSPM1, SYSMMU_DSPM1_QCH, "GATE_SYSMMU_DSPM1", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_DSPM, SYSREG_DSPM_QCH, "GATE_SYSREG_DSPM", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_VGEN_LITE_DSPM, VGEN_LITE_DSPM_QCH, "GATE_VGEN_LITE_DSPM", "UMUX_CLKCMU_DSPM_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_dsps_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_DSPS_BUS, MUX_CLKCMU_DSPS_BUS_USER, "UMUX_CLKCMU_DSPS_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_DSPS_AUD, MUX_CLKCMU_DSPS_AUD_USER, "UMUX_CLKCMU_DSPS_AUD", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_SCORE_BARON, SCORE_BARON_QCH, "GATE_SCORE_BARON", "UMUX_CLKCMU_DSPS_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_fsys0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_BUS, MUX_CLKCMU_FSYS0_BUS_USER, "UMUX_CLKCMU_FSYS0_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_DPGTC, MUX_CLKCMU_FSYS0_DPGTC_USER, "UMUX_CLKCMU_FSYS0_DPGTC", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0_PCIE, MUX_CLKCMU_FSYS0_PCIE_USER, "UMUX_CLKCMU_FSYS0_PCIE", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_DP_LINK, DP_LINK_QCH, "GATE_DP_LINK", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DP_LINK_GTC, DP_LINK_QCH_GTC, "GATE_DP_LINK_GTC", "UMUX_CLKCMU_FSYS0_DPGTC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_FSYS0, GPIO_FSYS0_QCH, "GATE_GPIO_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_DBI_A, PCIE_GEN3_QCH_DBI_A, "GATE_PCIE_GEN3_DBI_A", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_MSTR_SLV_A, PCIE_GEN3_QCH_MSTR_SLV_A, "GATE_PCIE_GEN3_MSTR_SLV_A", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_APB_A, PCIE_GEN3_QCH_APB_A, "GATE_PCIE_GEN3_APB_A", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_DBI_B, PCIE_GEN3_QCH_DBI_B, "GATE_PCIE_GEN3_DBI_B", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_MSTR_SLV_B, PCIE_GEN3_QCH_MSTR_SLV_B, "GATE_PCIE_GEN3_MSTR_SLV_B", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_APB_B, PCIE_GEN3_QCH_APB_B, "GATE_PCIE_GEN3_APB_B", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_SCLK, PCIE_GEN3_QCH_SCLK, "GATE_PCIE_GEN3_SCLK", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_PCS_APB, PCIE_GEN3_QCH_PCS_APB, "GATE_PCIE_GEN3_QCH_PCS_APB", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_IF_CMN, PCIE_GEN3_QCH_IF_CMN, "GATE_PCIE_GEN3_IF_CMN", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_IF_LN0, PCIE_GEN3_QCH_IF_LN0, "GATE_PCIE_GEN3_IF_LN0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN3_IF_LN1, PCIE_GEN3_QCH_IF_LN1, "GATE_PCIE_GEN3_IF_LN1", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_IA_GEN3A, PCIE_IA_GEN3A_QCH, "GATE_PCIE_IA_GEN3A", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_IA_GEN3B, PCIE_IA_GEN3B_QCH, "GATE_PCIE_IA_GEN3B", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_PCIE_GEN3A, SYSMMU_PCIE_GEN3A_QCH, "GATE_SYSMMU_PCIE_GEN3A", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_PCIE_GEN3B, SYSMMU_PCIE_GEN3B_QCH, "GATE_SYSMMU_PCIE_GEN3B", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_FSYS0, SYSREG_FSYS0_QCH, "GATE_SYSREG_FSYS0", "UMUX_CLKCMU_FSYS0_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_fsys0a_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS0A_BUS, MUX_CLKCMU_FSYS0A_BUS_USER, "UMUX_CLKCMU_FSYS0A_BUS", "UMUX_CLKCMU_FSYS0_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS0A_USBDP_DEBUG, MUX_CLKCMU_FSYS0A_USBDP_DEBUG_USER, "UMUX_CLKCMU_FSYS0A_USBDP_DEBUG", "UMUX_CLKCMU_FSYS0A_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_USB31DRD_REF, USB31DRD_QCH_REF, "GATE_USB31DRD_QCH_REF", "UMUX_CLKCMU_FSYS0A_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB31DRD_SLV_CTRL, USB31DRD_QCH_SLV_CTRL, "GATE_USB31DRD_QCH_SLV_CTRL", "UMUX_CLKCMU_FSYS0A_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB31DRD_SLV_LINK, USB31DRD_QCH_SLV_LINK, "GATE_USB31DRD_QCH_SLV_LINK", "UMUX_CLKCMU_FSYS0A_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB31DRD_APB, USB31DRD_QCH_APB, "GATE_USB31DRD_QCH_APB", "UMUX_CLKCMU_FSYS0A_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USB31DRD_PCS, USB31DRD_QCH_PCS, "GATE_USB31DRD_QCH_PCS", "UMUX_CLKCMU_FSYS0A_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_fsys1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_BUS, MUX_CLKCMU_FSYS1_BUS_USER, "UMUX_CLKCMU_FSYS1_BUS", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_MMC_CARD, MUX_CLKCMU_FSYS1_MMC_CARD_USER, "UMUX_CLKCMU_FSYS1_MMC_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_PCIE, MUX_CLKCMU_FSYS1_PCIE_USER, "UMUX_CLKCMU_FSYS1_PCIE", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_CARD, MUX_CLKCMU_FSYS1_UFS_CARD_USER, "UMUX_CLKCMU_FSYS1_UFS_CARD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_FSYS1_UFS_EMBD, MUX_CLKCMU_FSYS1_UFS_EMBD_USER, "UMUX_CLKCMU_FSYS1_UFS_EMBD", "UMUX_CLKCMU_FSYS1_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_MMC_CARD, MMC_CARD_QCH, "GATE_MMC_CARD", "UMUX_CLKCMU_FSYS1_MMC_CARD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_MSTR, PCIE_GEN2_QCH_MSTR, "GATE_PCIE_GEN2_QCH_MSTR", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_PCS, PCIE_GEN2_QCH_PCS, "GATE_PCIE_GEN2_QCH_PCS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_PHY, PCIE_GEN2_QCH_PHY, "GATE_PCIE_GEN2_QCH_PHY", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_DBI, PCIE_GEN2_QCH_DBI, "GATE_PCIE_GEN2_QCH_DBI", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_APB, PCIE_GEN2_QCH_APB, "GATE_PCIE_GEN2_QCH_APB", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PCIE_GEN2_SOCPLL, PCIE_GEN2_QCH_SOCPLL, "GATE_PCIE_GEN2_QCH_SOCPLL", "UMUX_CLKCMU_FSYS1_PCIE", 0, VCLK_GATE | VCLK_QCH_DIS, NULL),
	HWACG_VCLK(GATE_PCIE_IA_GEN2, PCIE_IA_GEN2_QCH, "GATE_PCIE_IA_GEN2", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_RTIC, RTIC_QCH, "GATE_RTIC", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SSS, SSS_QCH, "GATE_SSS", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_FSYS1, SYSMMU_FSYS1_QCH, "GATE_SYSMMU_FSYS1", "UMUX_CLKCMU_FSYS1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_CARD, UFS_CARD_QCH, "GATE_UFS_CARD", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_CARD_FMP, UFS_CARD_QCH_FMP, "GATE_UFS_CARD_QCH_FMP", "UMUX_CLKCMU_FSYS1_UFS_CARD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_EMBD, UFS_EMBD_QCH, "GATE_UFS_EMBD", "UMUX_CLKCMU_FSYS1_UFS_EMBD", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UFS_EMBD_FMP, UFS_EMBD_QCH_FMP, "GATE_UFS_EMBD_QCH_FMP", "UMUX_CLKCMU_FSYS1_UFS_EMBD", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_g2d_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D_USER, "UMUX_CLKCMU_G2D_G2D", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL_USER, "UMUX_CLKCMU_G2D_MSCL", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_G2D, G2D_QCH, "GATE_G2D", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_JPEG, JPEG_QCH, "GATE_JPEG", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_JSQZ, JSQZ_QCH, "GATE_JSQZ", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MSCL, MSCL_QCH, "GATE_MSCL", "UMUX_CLKCMU_G2D_MSCL", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_G2DD0, SYSMMU_G2DD0_QCH, "GATE_SYSMMU_G2DD0", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_G2DD1, SYSMMU_G2DD1_QCH, "GATE_SYSMMU_G2DD1", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_G2DD2, SYSMMU_G2DD2_QCH, "GATE_SYSMMU_G2DD2", "UMUX_CLKCMU_G2D_G2D", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_g3d_hwacg_vclks[] __initdata = {
	HWACG_VCLK(GATE_GPU, GPU_QCH, "GATE_GPU", NULL, 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_isphq_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_ISPHQ_BUS, MUX_CLKCMU_ISPHQ_BUS_USER, "UMUX_CLKCMU_ISPHQ_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_ISPHQ_CMU_ISPHQ, ISPHQ_CMU_ISPHQ_QCH, "GATE_ISPHQ_CMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_ISPHQ, IS_ISPHQ_QCH_ISPHQ, "GATE_IS_ISPHQ_QCH_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_SYSMMU_ISPHQ, IS_ISPHQ_QCH_SYSMMU_ISPHQ, "GATE_IS_ISPHQ_QCH_SYSMMU_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_VGEN_LITE_ISPHQ, IS_ISPHQ_QCH_VGEN_LITE_ISPHQ, "GATE_IS_ISPHQ_QCH_VGEN_LITE_ISPHQ", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPHQ_ISPHQ_C2COM, IS_ISPHQ_QCH_ISPHQ_C2COM, "GATE_IS_ISPHQ_QCH_ISPHQ_C2COM", "UMUX_CLKCMU_ISPHQ_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_isplp_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_ISPLP_BUS, MUX_CLKCMU_ISPLP_BUS_USER, "UMUX_CLKCMU_ISPLP_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_ISPLP_GDC, MUX_CLKCMU_ISPLP_GDC_USER, "UMUX_CLKCMU_ISPLP_GDC", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_IS_ISPLP_MC_SCALER, IS_ISPLP_QCH_MC_SCALER, "GATE_IS_ISPLP_QCH_MC_SCALER", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_ISPLP, IS_ISPLP_QCH_ISPLP, "GATE_IS_ISPLP_QCH_ISPLP", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_SYSMMU_ISPLP0, IS_ISPLP_QCH_SYSMMU_ISPLP0, "GATE_IS_ISPLP_QCH_SYSMMU_ISPLP0", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_SYSMMU_ISPLP1, IS_ISPLP_QCH_SYSMMU_ISPLP1, "GATE_IS_ISPLP_QCH_SYSMMU_ISPLP1", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_GDC, IS_ISPLP_QCH_GDC, "GATE_IS_ISPLP_QCH_GDC", "UMUX_CLKCMU_ISPLP_GDC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_VGEN_LITE, IS_ISPLP_QCH_VGEN_LITE, "GATE_IS_ISPLP_QCH_VGEN_LITE", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPLP_ISPLP_C2, IS_ISPLP_QCH_ISPLP_C2, "GATE_IS_ISPLP_QCH_ISPLP_C2", "UMUX_CLKCMU_ISPLP_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_isppre_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_ISPPRE_BUS, MUX_CLKCMU_ISPPRE_BUS_USER, "UMUX_CLKCMU_ISPPRE_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_IS_ISPPRE_CSIS0, IS_ISPPRE_QCH_CSIS0, "GATE_IS_ISPPRE_QCH_CSIS0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_CSIS1, IS_ISPPRE_QCH_CSIS1, "GATE_IS_ISPPRE_QCH_CSIS1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_CSIS2, IS_ISPPRE_QCH_CSIS2, "GATE_IS_ISPPRE_QCH_CSIS2", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_CSIS3, IS_ISPPRE_QCH_CSIS3, "GATE_IS_ISPPRE_QCH_CSIS3", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_PDP_TOP_DMA, IS_ISPPRE_QCH_PDP_TOP_DMA, "GATE_IS_ISPPRE_QCH_PDP_TOP_DMA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_SYSMMU_ISPPRE, IS_ISPPRE_QCH_SYSMMU_ISPPRE, "GATE_IS_ISPPRE_QCH_SYSMMU_ISPPRE", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_3AA0, IS_ISPPRE_QCH_3AA0, "GATE_IS_ISPPRE_QCH_3AA0", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_3AA1, IS_ISPPRE_QCH_3AA1, "GATE_IS_ISPPRE_QCH_3AA1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_PDP_TOP_CORE_TOP, IS_ISPPRE_QCH_PDP_TOP_CORE_TOP, "GATE_IS_ISPPRE_QCH_PDP_TOP_CORE_TOP", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_VGEN_LITE, IS_ISPPRE_QCH_VGEN_LITE, "GATE_IS_ISPPRE_QCH_VGEN_LITE", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_VGEN_LITE1, IS_ISPPRE_QCH_VGEN_LITE1, "GATE_IS_ISPPRE_QCH_VGEN_LITE1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_CSIS3_1, IS_ISPPRE_QCH_QSIS3_1, "GATE_IS_ISPPRE_QCH_CSIS3_1", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_CSISX4_PDP_DMA, IS_ISPPRE_QCH_CSISX4_PDP_DMA, "GATE_IS_ISPPRE_QCH_CSISX4_PDP_DMA", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_VGEN_LITE2, IS_ISPPRE_QCH_VGEN_LITE2, "GATE_IS_ISPPRE_QCH_VGEN_LITE2", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IS_ISPPRE_QCH_VPP, IS_ISPPRE_QCH_VPP, "GATE_IS_ISPPRE_QCH_VPP", "UMUX_CLKCMU_ISPPRE_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_iva_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_IVA_BUS, MUX_CLKCMU_IVA_BUS_USER, "UMUX_CLKCMU_IVA_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_IVA_IVA, IVA_QCH_IVA, "GATE_IVA_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IVA_IVA_DEBUG, IVA_QCH_IVA_DEBUG, "GATE_IVA_IVA_DEBUG", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_IVA_INTMEM, IVA_INTMEM_QCH, "GATE_IVA_INTMEM", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_IVA, SYSMMU_IVA_QCH, "GATE_SYSMMU_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TREX_RB1_IVA, TREX_RB1_IVA_QCH, "GATE_TREX_RB1_IVA", "UMUX_CLKCMU_IVA_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_mfc_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC_USER, "UMUX_CLKCMU_MFC_MFC", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_MFC_WFD, MUX_CLKCMU_MFC_WFD_USER, "UMUX_CLKCMU_MFC_WFD", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_MFC, MFC_QCH, "GATE_MFC", "UMUX_CLKCMU_MFC_MFC", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_MFCD0, SYSMMU_MFCD0_QCH, "GATE_SYSMMU_MFCD0", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_MFCD1, SYSMMU_MFCD1_QCH, "GATE_SYSMMU_MFCD1", NULL, 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WFD, WFD_QCH, "GATE_WFD", "UMUX_CLKCMU_MFC_WFD", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_npu0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_NPU0_BUS, MUX_CLKCMU_NPU0_BUS_USER, "UMUX_CLKCMU_NPU0_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_NPU0_CPU, MUX_CLKCMU_NPU0_CPU_USER, "UMUX_CLKCMU_NPU0_CPU", "UMUX_CLKCMU_NPU0_BUS", 0, 0, NULL),

	HWACG_VCLK(GATE_NPUC, NPUC_QCH, "GATE_NPUC", "UMUX_CLKCMU_NPU0_CPU", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_NPUD_UNIT0, NPUD_UNIT0_QCH, "GATE_NPUD_UNIT0", "UMUX_CLKCMU_NPU0_CPU", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SMMU_NPU0, SMMU_NPU0_QCH, "GATE_SMMU_NPU0", "UMUX_CLKCMU_NPU0_CPU", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_npu1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_NPU1_BUS, MUX_CLKCMU_NPU1_BUS_USER, "UMUX_CLKCMU_NPU1_BUS", NULL, 0, 0, NULL),
};

struct init_vclk exynos9820_peric0_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_BUS, MUX_CLKCMU_PERIC0_BUS_USER, "UMUX_CLKCMU_PERIC0_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI_I2C, MUX_CLKCMU_PERIC0_USI_I2C_USER, "UMUX_CLKCMU_PERIC0_USI_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_GPIO_PERIC0, GPIO_PERIC0_QCH, "GATE_GPIO_PERIC0", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PWM, PWM_QCH, "GATE_PWM", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UART_DBG, UART_DBG_QCH, "GATE_UART_DBG", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, "console-pclk0"),
	HWACG_VCLK(GATE_USI00_I2C, USI00_I2C_QCH, "GATE_USI00_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
#ifdef CONFIG_SENSORS_FINGERPRINT
	HWACG_VCLK(GATE_USI00_USI, USI00_USI_QCH, "GATE_USI00_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, "fp-spi-pclk"),
#else
	HWACG_VCLK(GATE_USI00_USI, USI00_USI_QCH, "GATE_USI00_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
#endif
	HWACG_VCLK(GATE_USI01_I2C, USI01_I2C_QCH, "GATE_USI01_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI01_USI, USI01_USI_QCH, "GATE_USI01_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI02_I2C, USI02_I2C_QCH, "GATE_USI02_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI02_USI, USI02_USI_QCH, "GATE_USI02_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI03_I2C, USI03_I2C_QCH, "GATE_USI03_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI03_USI, USI03_USI_QCH, "GATE_USI03_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI04_I2C, USI04_I2C_QCH, "GATE_USI04_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI04_USI, USI04_USI_QCH, "GATE_USI04_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI05_I2C, USI05_I2C_QCH, "GATE_USI05_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI05_USI, USI05_USI_QCH, "GATE_USI05_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI12_I2C, USI12_I2C_QCH, "GATE_USI12_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI12_USI, USI12_USI_QCH, "GATE_USI12_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI13_I2C, USI13_I2C_QCH, "GATE_USI13_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI13_USI, USI13_USI_QCH, "GATE_USI13_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI14_I2C, USI14_I2C_QCH, "GATE_USI14_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI14_USI, USI14_USI_QCH, "GATE_USI14_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI15_I2C, USI15_I2C_QCH, "GATE_USI15_I2C", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI15_USI, USI15_USI_QCH, "GATE_USI15_USI", "UMUX_CLKCMU_PERIC0_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_peric1_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_BUS, MUX_CLKCMU_PERIC1_BUS_USER, "UMUX_CLKCMU_PERIC1_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_PERIC1_USI_I2C, MUX_CLKCMU_PERIC1_USI_I2C_USER, "UMUX_CLKCMU_PERIC1_USI_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),

	HWACG_VCLK(GATE_GPIO_PERIC1, GPIO_PERIC1_QCH, "GATE_GPIO_PERIC1", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CAM0, I2C_CAM0_QCH, "GATE_I2C_CAM0", "UMUX_CLKCMU_PERIC1_I2C_CAM0", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CAM1, I2C_CAM1_QCH, "GATE_I2C_CAM1", "UMUX_CLKCMU_PERIC1_I2C_CAM1", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CAM2, I2C_CAM2_QCH, "GATE_I2C_CAM2", "UMUX_CLKCMU_PERIC1_I2C_CAM2", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I2C_CAM3, I2C_CAM3_QCH, "GATE_I2C_CAM3", "UMUX_CLKCMU_PERIC1_I2C_CAM3", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I3C_I3C, I3C_QCH_I3C, "GATE_I3C_QCH_I3C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_I3C_DMY, I3C_QCH_DMY, "GATE_I3C_QCH_DMY", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SPI_CAM0, SPI_CAM0_QCH, "GATE_SPI_CAM0", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_UART_BT, UART_BT_QCH, "GATE_UART_BT", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI06_I2C, USI06_I2C_QCH, "GATE_USI06_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI06_USI, USI06_USI_QCH, "GATE_USI06_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI07_I2C, USI07_I2C_QCH, "GATE_USI07_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI07_USI, USI07_USI_QCH, "GATE_USI07_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI08_I2C, USI08_I2C_QCH, "GATE_USI08_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI08_USI, USI08_USI_QCH, "GATE_USI08_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI09_I2C, USI09_I2C_QCH, "GATE_USI09_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI09_USI, USI09_USI_QCH, "GATE_USI09_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI10_I2C, USI10_I2C_QCH, "GATE_USI10_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI10_USI, USI10_USI_QCH, "GATE_USI10_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI11_I2C, USI11_I2C_QCH, "GATE_USI11_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI11_USI, USI11_USI_QCH, "GATE_USI11_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI16_I3C_DMY, USI16_I3C_QCH_DMY, "GATE_USI16_I3C_QCH_DMY", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI16_I3C_I3C, USI16_I3C_QCH_I3C, "GATE_USI16_I3C_QCH_I3C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI16_USI, USI16_USI_QCH, "GATE_USI16_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI17_I2C, USI17_I2C_QCH, "GATE_USI17_I2C", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_USI17_USI, USI17_USI_QCH, "GATE_USI17_USI", "UMUX_CLKCMU_PERIC1_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_peris_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_PERIS_BUS, MUX_CLKCMU_PERIS_BUS_USER, "UMUX_CLKCMU_PERIS_BUS", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_GIC, GIC_QCH, "GATE_GIC", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MCT, MCT_QCH, "GATE_MCT", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_BIRA, OTP_CON_BIRA_QCH, "GATE_OTP_CON_BIRA", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_BISR, OTP_CON_BISR_QCH, "GATE_OTP_CON_BISR", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_OTP_CON_TOP, OTP_CON_TOP_QCH, "GATE_OTP_CON_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_PERIS_CMU_PERIS, PERIS_CMU_PERIS_QCH, "GATE_PERIS_CMU_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_PERIS, SYSREG_PERIS_QCH, "GATE_SYSREG_PERIS", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TMU_SUB, TMU_SUB_QCH, "GATE_TMU_SUB", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TMU_TOP, TMU_TOP_QCH, "GATE_TMU_TOP", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER0, WDT_CLUSTER0_QCH, "GATE_WDT_CLUSTER0", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_CLUSTER2, WDT_CLUSTER2_QCH, "GATE_WDT_CLUSTER2", "UMUX_CLKCMU_PERIS_BUS", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_vra2_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_VRA2_BUS, MUX_CLKCMU_VRA2_BUS_USER, "UMUX_CLKCMU_VRA2_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_VRA2_STR, MUX_CLKCMU_VRA2_STR_USER, "UMUX_CLKCMU_VRA2_STR", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_VRA2, VRA2_QCH, "GATE_VRA2", "UMUX_CLKCMU_VRA2_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSMMU_VRA2, SYSMMU_VRA2_QCH, "GATE_SYSMMU_VRA2", "UMUX_CLKCMU_VRA2_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_STR, STR_QCH, "GATE_STR", "UMUX_CLKCMU_VRA2_STR", 0, VCLK_GATE, NULL),
};

struct init_vclk exynos9820_vts_hwacg_vclks[] __initdata = {
	HWACG_VCLK(UMUX_CLKCMU_VTS_BUS, MUX_CLKCMU_VTS_BUS_USER, "UMUX_CLKCMU_VTS_BUS", NULL, 0, 0, NULL),
	HWACG_VCLK(UMUX_CLKCMU_VTS_RCO, MUX_CLKCMU_VTS_RCO_USER, "UMUX_CLKCMU_VTS_RCO", NULL, 0, 0, NULL),

	HWACG_VCLK(GATE_CORTEXM4INTEGRATION_CPU, CORTEXM4INTEGRATION_QCH_CPU, "GATE_CORTEXM4INTEGRATION_CPU", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF_PCLK, DMIC_IF_QCH_PCLK, "GATE_DMIC_IF_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF_DMIC_CLK, DMIC_IF_QCH_DMIC_CLK, "GATE_DMIC_IF_DMIC_CLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF_3RD_PCLK, DMIC_IF_3RD_QCH_PCLK, "GATE_DMIC_IF_3RD_PCLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_DMIC_IF_3RD_DMIC_CLK, DMIC_IF_3RD_QCH_DMIC_CLK, "GATE_DMIC_IF_3RD_DMIC_CLK", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_GPIO_VTS, GPIO_VTS_QCH, "GATE_GPIO_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HWACG_SYS_DMIC0, HWACG_SYS_DMIC0_QCH, "GATE_HWACG_SYS_DMIC0", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HWACG_SYS_DMIC1, HWACG_SYS_DMIC1_QCH, "GATE_HWACG_SYS_DMIC1", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HWACG_SYS_DMIC2, HWACG_SYS_DMIC2_QCH, "GATE_HWACG_SYS_DMIC2", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_HWACG_SYS_DMIC3, HWACG_SYS_DMIC3_QCH, "GATE_HWACG_SYS_DMIC3", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_ABOX_VTS, MAILBOX_ABOX_VTS_QCH, "GATE_MAILBOX_ABOX_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_MAILBOX_AP_VTS, MAILBOX_AP_VTS_QCH, "GATE_MAILBOX_AP_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SWEEPER_C_VTS, SWEEPER_C_VTS_QCH, "GATE_SWEEPER_C_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_SYSREG_VTS, SYSREG_VTS_QCH, "GATE_SYSREG_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_TIMER_VTS, TIMER_QCH, "GATE_TIMER_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
	HWACG_VCLK(GATE_WDT_VTS, WDT_VTS_QCH, "GATE_WDT_VTS", "UMUX_CLKCMU_VTS_BUS", 0, VCLK_GATE, NULL),
};

/* Special VCLK */
struct init_vclk exynos9820_apm_vclks[] __initdata = {
	VCLK(DOUT_CLKCMU_VTS_BUS, CLKCMU_VTS_BUS, "DOUT_CLKCMU_VTS_BUS", 0, 0, NULL),
	VCLK(DOUT_CLKCMU_CMGP_BUS, CLKCMU_CMGP_BUS, "DOUT_CLKCMU_CMGP_BUS", 0, 0, NULL),
};

struct init_vclk exynos9820_abox_vclks[] __initdata = {
	VCLK(DOUT_CLK_AUD_AUDIF, DIV_CLK_AUD_AUDIF, "DOUT_CLK_AUD_AUDIF", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_DSIF, DIV_CLK_AUD_DSIF, "DOUT_CLK_AUD_DSIF", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_UAIF0, DIV_CLK_AUD_UAIF0, "DOUT_CLK_AUD_UAIF0", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_UAIF1, DIV_CLK_AUD_UAIF1, "DOUT_CLK_AUD_UAIF1", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_UAIF2, DIV_CLK_AUD_UAIF2, "DOUT_CLK_AUD_UAIF2", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_UAIF3, DIV_CLK_AUD_UAIF3, "DOUT_CLK_AUD_UAIF3", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_CPU_ACLK, DIV_CLK_AUD_CPU_ACLK, "DOUT_CLK_AUD_CPU_ACLK", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_BUS, DIV_CLK_AUD_BUS, "DOUT_CLK_AUD_BUS", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_BUSP, DIV_CLK_AUD_BUSP, "DOUT_CLK_AUD_BUSP", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_DMIC, DIV_CLK_AUD_DMIC, "DOUT_CLK_AUD_DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_CNT, DIV_CLK_AUD_CNT, "DOUT_CLK_AUD_CNT", 0, 0, NULL),
	VCLK(DOUT_CLK_AUD_MCLK, DIV_CLK_AUD_MCLK, "DOUT_CLK_AUD_MCLK", 0, 0, NULL),
	VCLK(PLL_OUT_AUD0, PLL_AUD0, "PLL_OUT_AUD0", 0, 0, NULL),
	VCLK(PLL_OUT_AUD1, PLL_AUD1, "PLL_OUT_AUD1", 0, 0, NULL),
	VCLK(PLL_OUT_MMC, PLL_MMC, "PLL_OUT_MMC", 0, 0, NULL),
};

struct init_vclk exynos9820_cmgp_vclks[] __initdata = {
	VCLK(DOUT_CLK_I2C_CMGP0, DIV_CLK_I2C_CMGP0, "DOUT_CLK_I2C_CMGP0", 0, 0, NULL),
	VCLK(DOUT_CLK_USI_CMGP1, DIV_CLK_USI_CMGP1, "DOUT_CLK_USI_CMGP1", 0, 0, NULL),
	VCLK(DOUT_CLK_USI_CMGP0, VCLK_DIV_CLK_USI_CMGP0, "DOUT_CLK_USI_CMGP0", 0, 0, NULL),
	VCLK(DOUT_CLK_USI_CMGP2, DIV_CLK_USI_CMGP2, "DOUT_CLK_USI_CMGP2", 0, 0, NULL),
	VCLK(DOUT_CLK_USI_CMGP3, DIV_CLK_USI_CMGP3, "DOUT_CLK_USI_CMGP3", 0, 0, NULL),
	VCLK(DOUT_CLK_CMGP_ADC, DIV_CLK_CMGP_ADC, "DOUT_CLK_CMGP_ADC", 0, 0, NULL),
	VCLK(DOUT_CLK_I2C_CMGP1, DIV_CLK_I2C_CMGP1, "DOUT_CLK_I2C_CMGP1", 0, 0, NULL),
	VCLK(DOUT_CLK_I2C_CMGP2, DIV_CLK_I2C_CMGP2, "DOUT_CLK_I2C_CMGP2", 0, 0, NULL),
	VCLK(DOUT_CLK_I2C_CMGP3, DIV_CLK_I2C_CMGP3, "DOUT_CLK_I2C_CMGP3", 0, 0, NULL),
	VCLK(DOUT_CLK_CMGP_BUS, DIV_CLK_CMGP_BUS, "DOUT_CLK_CMGP_BUS", 0, 0, NULL),
};

struct init_vclk exynos9820_cmu_vclks[] __initdata = {
	VCLK(CIS_CLK0, CLKCMU_CIS_CLK0, "CIS_CLK0", 0, 0, NULL),
	VCLK(CIS_CLK1, CLKCMU_CIS_CLK1, "CIS_CLK1", 0, 0, NULL),
	VCLK(CIS_CLK2, CLKCMU_CIS_CLK2, "CIS_CLK2", 0, 0, NULL),
	VCLK(CIS_CLK3, CLKCMU_CIS_CLK3, "CIS_CLK3", 0, 0, NULL),
	VCLK(CIS_CLK4, CLKCMU_CIS_CLK4, "CIS_CLK4", 0, 0, NULL),
};

struct init_vclk exynos9820_peric0_vclks[] __initdata = {
#ifdef CONFIG_SENSORS_FINGERPRINT
	VCLK(DOUT_CLK_PERIC0_USI00_USI, VCLK_DIV_CLK_PERIC0_USI00_USI, "DOUT_CLK_PERIC0_USI00_USI", 0, 0, "fp-spi-sclk"),
#else
	VCLK(DOUT_CLK_PERIC0_USI00_USI, VCLK_DIV_CLK_PERIC0_USI00_USI, "DOUT_CLK_PERIC0_USI00_USI", 0, 0, NULL),
#endif
	VCLK(DOUT_CLK_PERIC0_USI01_USI, VCLK_DIV_CLK_PERIC0_USI01_USI, "DOUT_CLK_PERIC0_USI01_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI02_USI, VCLK_DIV_CLK_PERIC0_USI02_USI, "DOUT_CLK_PERIC0_USI02_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI03_USI, VCLK_DIV_CLK_PERIC0_USI03_USI, "DOUT_CLK_PERIC0_USI03_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI04_USI, VCLK_DIV_CLK_PERIC0_USI04_USI, "DOUT_CLK_PERIC0_USI04_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI05_USI, VCLK_DIV_CLK_PERIC0_USI05_USI, "DOUT_CLK_PERIC0_USI05_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI_I2C, DIV_CLK_PERIC0_USI_I2C, "DOUT_CLK_PERIC0_USI_I2C", 0, 0, NULL),
	VCLK(UART_DBG, VCLK_DIV_CLK_PERIC0_UART_DBG, "UART_DBG", 0, 0, "console-sclk0"),
	VCLK(DOUT_CLK_PERIC0_USI12_USI, VCLK_DIV_CLK_PERIC0_USI12_USI, "DOUT_CLK_PERIC0_USI12_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI13_USI, VCLK_DIV_CLK_PERIC0_USI13_USI, "DOUT_CLK_PERIC0_USI13_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI14_USI, VCLK_DIV_CLK_PERIC0_USI14_USI, "DOUT_CLK_PERIC0_USI14_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC0_USI15_USI, VCLK_DIV_CLK_PERIC0_USI15_USI, "DOUT_CLK_PERIC0_USI15_USI", 0, 0, NULL),
};

struct init_vclk exynos9820_peric1_vclks[] __initdata = {
	VCLK(DOUT_CLK_PERIC1_UART_BT, VCLK_DIV_CLK_PERIC1_UART_BT, "DOUT_CLK_PERIC1_UART_BT", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI_I2C, DIV_CLK_PERIC1_USI_I2C, "DOUT_CLK_PERIC1_USI_I2C", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI06_USI, VCLK_DIV_CLK_PERIC1_USI06_USI, "DOUT_CLK_PERIC1_USI06_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI07_USI, VCLK_DIV_CLK_PERIC1_USI07_USI, "DOUT_CLK_PERIC1_USI07_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI08_USI, VCLK_DIV_CLK_PERIC1_USI08_USI, "DOUT_CLK_PERIC1_USI08_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_I2C_CAM0, VCLK_DIV_CLK_PERIC1_I2C_CAM0, "DOUT_CLK_PERIC1_I2C_CAM0", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_I2C_CAM1, VCLK_DIV_CLK_PERIC1_I2C_CAM1, "DOUT_CLK_PERIC1_I2C_CAM1", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_I2C_CAM2, VCLK_DIV_CLK_PERIC1_I2C_CAM2, "DOUT_CLK_PERIC1_I2C_CAM2", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_I2C_CAM3, VCLK_DIV_CLK_PERIC1_I2C_CAM3, "DOUT_CLK_PERIC1_I2C_CAM3", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_SPI_CAM0, VCLK_DIV_CLK_PERIC1_SPI_CAM0, "DOUT_CLK_PERIC1_SPI_CAM0", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI09_USI, VCLK_DIV_CLK_PERIC1_USI09_USI, "DOUT_CLK_PERIC1_USI09_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI10_USI, VCLK_DIV_CLK_PERIC1_USI10_USI, "DOUT_CLK_PERIC1_USI10_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI11_USI, VCLK_DIV_CLK_PERIC1_USI11_USI, "DOUT_CLK_PERIC1_USI11_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI16_USI, VCLK_DIV_CLK_PERIC1_USI16_USI, "DOUT_CLK_PERIC1_USI16_USI", 0, 0, NULL),
	VCLK(DOUT_CLK_PERIC1_USI17_USI, VCLK_DIV_CLK_PERIC1_USI17_USI, "DOUT_CLK_PERIC1_USI17_USI", 0, 0, NULL),
};

struct init_vclk exynos9820_vra2_vclks[] __initdata = {
	VCLK(DOUT_CLK_VRA2_BUSP, DIV_CLK_VRA2_BUSP, "DOUT_CLK_VRA2_BUSP", 0, 0, NULL),
};

struct init_vclk exynos9820_vts_vclks[] __initdata = {
	VCLK(DOUT_CLK_VTS_DMIC_IF, DIV_CLK_VTS_DMIC_IF, "DOUT_CLK_VTS_DMIC_IF", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_DMIC, DIV_CLK_VTS_DMIC, "DOUT_CLK_VTS_DMIC", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_DMIC_DIV2, DIV_CLK_VTS_DMIC_DIV2, "DOUT_CLK_VTS_DMIC_DIV2", 0, 0, NULL),
	VCLK(DOUT_CLK_VTS_BUS, DIV_CLK_VTS_BUS, "DOUT_CLK_VTS_BUS", 0, 0, NULL),
};

struct init_vclk exynos9820_fsys1_vclks[] __initdata = {
	VCLK(DOUT_CLK_FSYS1_MMC_CARD, DIV_CLK_FSYS1_MMC_CARD, "DOUT_CLK_FSYS1_MMC_CARD", 0, 0, NULL),
	VCLK(UFS_EMBD, VCLK_CLKCMU_FSYS1_UFS_EMBD, "UFS_EMBD", 0, 0, NULL),
};

struct init_vclk exynos9820_fsys0a_vclks[] __initdata = {
	VCLK(USB31DRD, MUX_CLKCMU_FSYS0A_USB31DRD_USER, "USB31DRD", 0, 0, NULL),
};

struct init_vclk exynos9820_npu0_vclks[] __initdata = {
	VCLK(DOUT_CLK_NPU0_BUSP, DIV_CLK_NPU0_BUSP, "DOUT_CLK_NPU0_BUSP", 0, 0, NULL),
	VCLK(DOUT_CLK_NPU0_CPU, DIV_CLK_NPU0_CPU, "DOUT_CLK_NPU0_CPU", 0, 0, NULL),
};

struct init_vclk exynos9820_npu1_vclks[] __initdata = {
	VCLK(DOUT_CLK_NPU1_BUSP, DIV_CLK_NPU1_BUSP, "DOUT_CLK_NPU1_BUSP", 0, 0, NULL),
};

static struct init_vclk exynos9820_clkout_vclks[] __initdata = {
	VCLK(OSC_NFC, VCLK_CLKOUT1, "OSC_NFC", 0, 0, NULL),
	VCLK(OSC_AUD, VCLK_CLKOUT0, "OSC_AUD", 0, 0, NULL),
};

static __initdata struct of_device_id ext_clk_match[] = {
	{.compatible = "samsung,exynos9820-oscclk", .data = (void *)0},
	{},
};

void exynos9820_vclk_init(void)
{
	/* Common clock init */
}

/* register exynos9820 clocks */
void __init exynos9820_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	int ret;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	} else {
		panic("%s: unable to determine soc\n", __func__);
	}

	ret = cal_if_init(np);
	if (ret)
		panic("%s: unable to initialize cal-if\n", __func__);

	exynos9820_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!exynos9820_clk_provider)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_register_of_fixed_ext(exynos9820_clk_provider, exynos9820_fixed_rate_ext_clks,
					  ARRAY_SIZE(exynos9820_fixed_rate_ext_clks),
					  ext_clk_match);

	/* register HWACG vclk */
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_apm_hwacg_vclks, ARRAY_SIZE(exynos9820_apm_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_abox_hwacg_vclks, ARRAY_SIZE(exynos9820_abox_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_busc_hwacg_vclks, ARRAY_SIZE(exynos9820_busc_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_cmgp_hwacg_vclks, ARRAY_SIZE(exynos9820_cmgp_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_cmu_hwacg_vclks, ARRAY_SIZE(exynos9820_cmu_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_core_hwacg_vclks, ARRAY_SIZE(exynos9820_core_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_dpu_hwacg_vclks, ARRAY_SIZE(exynos9820_dpu_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_dspm_hwacg_vclks, ARRAY_SIZE(exynos9820_dspm_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_dsps_hwacg_vclks, ARRAY_SIZE(exynos9820_dsps_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_fsys0_hwacg_vclks, ARRAY_SIZE(exynos9820_fsys0_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_fsys0a_hwacg_vclks, ARRAY_SIZE(exynos9820_fsys0a_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_fsys1_hwacg_vclks, ARRAY_SIZE(exynos9820_fsys1_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_g2d_hwacg_vclks, ARRAY_SIZE(exynos9820_g2d_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_g3d_hwacg_vclks, ARRAY_SIZE(exynos9820_g3d_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_isphq_hwacg_vclks, ARRAY_SIZE(exynos9820_isphq_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_isplp_hwacg_vclks, ARRAY_SIZE(exynos9820_isplp_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_isppre_hwacg_vclks, ARRAY_SIZE(exynos9820_isppre_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_iva_hwacg_vclks, ARRAY_SIZE(exynos9820_iva_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_mfc_hwacg_vclks, ARRAY_SIZE(exynos9820_mfc_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_npu0_hwacg_vclks, ARRAY_SIZE(exynos9820_npu0_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_npu1_hwacg_vclks, ARRAY_SIZE(exynos9820_npu1_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_peric0_hwacg_vclks, ARRAY_SIZE(exynos9820_peric0_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_peric1_hwacg_vclks, ARRAY_SIZE(exynos9820_peric1_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_peris_hwacg_vclks, ARRAY_SIZE(exynos9820_peris_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_vra2_hwacg_vclks, ARRAY_SIZE(exynos9820_vra2_hwacg_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_vts_hwacg_vclks, ARRAY_SIZE(exynos9820_vts_hwacg_vclks));

	/* register special vclk */
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_apm_vclks, ARRAY_SIZE(exynos9820_apm_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_abox_vclks, ARRAY_SIZE(exynos9820_abox_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_cmgp_vclks, ARRAY_SIZE(exynos9820_cmgp_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_cmu_vclks, ARRAY_SIZE(exynos9820_cmu_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_peric0_vclks, ARRAY_SIZE(exynos9820_peric0_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_peric1_vclks, ARRAY_SIZE(exynos9820_peric1_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_vra2_vclks, ARRAY_SIZE(exynos9820_vra2_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_vts_vclks, ARRAY_SIZE(exynos9820_vts_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_fsys0a_vclks, ARRAY_SIZE(exynos9820_fsys0a_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_fsys1_vclks, ARRAY_SIZE(exynos9820_fsys1_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_npu0_vclks, ARRAY_SIZE(exynos9820_npu0_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_npu1_vclks, ARRAY_SIZE(exynos9820_npu1_vclks));
	samsung_register_vclk(exynos9820_clk_provider, exynos9820_clkout_vclks, ARRAY_SIZE(exynos9820_clkout_vclks));

	clk_register_fixed_factor(NULL, "pwm-clock", "fin_pll", CLK_SET_RATE_PARENT, 1, 1);

	samsung_clk_of_add_provider(np, exynos9820_clk_provider);

	late_time_init = exynos9820_vclk_init;

	pr_info("EXYNOS9820: Clock setup completed\n");
}

CLK_OF_DECLARE(exynos9820_clk, "samsung,exynos9820-clock", exynos9820_clk_init);